Create main.py
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Sam Sneed
GitHub
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177
main.py
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177
main.py
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from capstone import *
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from keystone import *
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import argparse
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# Disassemble x86_64 binary
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def disassemble_x86_64(binary_path):
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with open(binary_path, 'rb') as f:
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code = f.read()
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md = Cs(CS_ARCH_X86, CS_MODE_64)
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instructions = list(md.disasm(code, 0x1000))
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return instructions
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# Translate x86_64 instructions to ARM64
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def translate_instructions(x86_instructions):
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translated_instructions = []
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for ins in x86_instructions:
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arm64_instruction = translate_x86_to_arm64(ins)
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translated_instructions.extend(arm64_instruction)
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return translated_instructions
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# Assemble ARM64 instructions into binary
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def assemble_arm64(instructions, output_path):
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ks = Ks(KS_ARCH_ARM64, KS_MODE_ARM)
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encoding, count = ks.asm('\n'.join(instructions))
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with open(output_path, 'wb') as f:
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f.write(bytearray(encoding))
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# Extended translation logic for x86_64 to ARM64
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def translate_x86_to_arm64(x86_ins):
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reg_mapping = {
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'rax': 'x0', 'rbx': 'x1', 'rcx': 'x2', 'rdx': 'x3',
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'rsi': 'x4', 'rdi': 'x5', 'rbp': 'x6', 'rsp': 'x7',
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'r8': 'x8', 'r9': 'x9', 'r10': 'x10', 'r11': 'x11',
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'r12': 'x12', 'r13': 'x13', 'r14': 'x14', 'r15': 'x15',
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'r16': 'x16', 'r17': 'x17', 'r18': 'x18', 'r19': 'x19',
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'r20': 'x20', 'r21': 'x21', 'r22': 'x22', 'r23': 'x23',
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'r24': 'x24', 'r25': 'x25', 'r26': 'x26', 'r27': 'x27',
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'r28': 'x28', 'r29': 'x29', 'r30': 'x30'
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}
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arm64_instructions = []
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def generate_arm64_instruction(opcode, operands):
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return f"{opcode} {' ,'.join(operands)}"
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def handle_immediate(operand):
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if operand.startswith('0x'):
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return f'#{operand}'
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return operand
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def parse_operands(op_str):
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return [op.strip() for op in op_str.split(',')]
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if x86_ins.mnemonic == 'mov':
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operands = parse_operands(x86_ins.op_str)
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if operands[0] in reg_mapping and operands[1] in reg_mapping:
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arm64_instructions.append(generate_arm64_instruction('mov', [reg_mapping[operands[0]], reg_mapping[operands[1]]]))
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elif operands[1].startswith('0x'):
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arm64_instructions.append(generate_arm64_instruction('mov', [reg_mapping[operands[0]], handle_immediate(operands[1])]))
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elif x86_ins.mnemonic == 'add':
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operands = parse_operands(x86_ins.op_str)
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if len(operands) == 2 and operands[0] in reg_mapping and operands[1] in reg_mapping:
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arm64_instructions.append(generate_arm64_instruction('add', [reg_mapping[operands[0]], reg_mapping[operands[0]], reg_mapping[operands[1]]]))
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elif len(operands) == 3 and operands[0] in reg_mapping and operands[1] in reg_mapping and operands[2] in reg_mapping:
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arm64_instructions.append(generate_arm64_instruction('add', [reg_mapping[operands[0]], reg_mapping[operands[1]], reg_mapping[operands[2]]]))
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elif x86_ins.mnemonic == 'sub':
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operands = parse_operands(x86_ins.op_str)
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if len(operands) == 2 and operands[0] in reg_mapping and operands[1] in reg_mapping:
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arm64_instructions.append(generate_arm64_instruction('sub', [reg_mapping[operands[0]], reg_mapping[reg_mapping[operands[1]]], handle_immediate('0')]))
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elif len(operands) == 3 and operands[0] in reg_mapping and operands[1] in reg_mapping and operands[2] in reg_mapping:
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arm64_instructions.append(generate_arm64_instruction('sub', [reg_mapping[operands[0]], reg_mapping[operands[1]], reg_mapping[operands[2]]]))
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elif x86_ins.mnemonic == 'mul':
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operands = parse_operands(x86_ins.op_str)
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if len(operands) == 2 and operands[0] in reg_mapping and operands[1] in reg_mapping:
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arm64_instructions.append(generate_arm64_instruction('mul', [reg_mapping[operands[0]], reg_mapping[operands[1]]]))
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elif x86_ins.mnemonic == 'div':
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operands = parse_operands(x86_ins.op_str)
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if len(operands) == 2 and operands[0] in reg_mapping and operands[1] in reg_mapping:
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arm64_instructions.append(generate_arm64_instruction('udiv', [reg_mapping[operands[0]], reg_mapping[operands[1]]]))
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elif x86_ins.mnemonic == 'nop':
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arm64_instructions.append('nop')
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elif x86_ins.mnemonic == 'cmp':
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operands = parse_operands(x86_ins.op_str)
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if len(operands) == 2 and operands[0] in reg_mapping and operands[1] in reg_mapping:
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arm64_instructions.append(generate_arm64_instruction('cmp', [reg_mapping[operands[0]], reg_mapping[operands[1]]]))
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elif x86_ins.mnemonic == 'jmp':
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arm64_instructions.append(f'b {x86_ins.op_str}')
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elif x86_ins.mnemonic == 'call':
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arm64_instructions.append(f'bl {x86_ins.op_str}')
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elif x86_ins.mnemonic == 'ret':
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arm64_instructions.append('ret')
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elif x86_ins.mnemonic == 'push':
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operands = parse_operands(x86_ins.op_str)
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if operands[0] in reg_mapping:
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arm64_instructions.append(f'stmd sp!, {{{reg_mapping[operands[0]]}}}')
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elif x86_ins.mnemonic == 'pop':
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operands = parse_operands(x86_ins.op_str)
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if operands[0] in reg_mapping:
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arm64_instructions.append(f'ldmd sp!, {{{reg_mapping[operands[0]]}}}')
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elif x86_ins.mnemonic == 'and':
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operands = parse_operands(x86_ins.op_str)
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if len(operands) == 3 and operands[0] in reg_mapping and operands[1] in reg_mapping:
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arm64_instructions.append(generate_arm64_instruction('and', [reg_mapping[operands[0]], reg_mapping[operands[1]], handle_immediate(operands[2])]))
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elif x86_ins.mnemonic == 'or':
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operands = parse_operands(x86_ins.op_str)
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if len(operands) == 3 and operands[0] in reg_mapping and operands[1] in reg_mapping:
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arm64_instructions.append(generate_arm64_instruction('orr', [reg_mapping[operands[0]], reg_mapping[operands[1]], handle_immediate(operands[2])]))
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elif x86_ins.mnemonic == 'xor':
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operands = parse_operands(x86_ins.op_str)
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if len(operands) == 3 and operands[0] in reg_mapping and operands[1] in reg_mapping:
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arm64_instructions.append(generate_arm64_instruction('eor', [reg_mapping[operands[0]], reg_mapping[operands[1]], handle_immediate(operands[2])]))
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elif x86_ins.mnemonic == 'shl':
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operands = parse_operands(x86_ins.op_str)
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if len(operands) == 2 and operands[0] in reg_mapping and operands[1] in reg_mapping:
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arm64_instructions.append(generate_arm64_instruction('lsl', [reg_mapping[operands[0]], reg_mapping[operands[1]], handle_immediate('1')]))
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elif x86_ins.mnemonic == 'shr':
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operands = parse_operands(x86_ins.op_str)
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if len(operands) == 2 and operands[0] in reg_mapping and operands[1] in reg_mapping:
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arm64_instructions.append(generate_arm64_instruction('lsr', [reg_mapping[operands[0]], reg_mapping[operands[1]], handle_immediate('1')]))
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elif x86_ins.mnemonic == 'sar':
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operands = parse_operands(x86_ins.op_str)
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if len(operands) == 2 and operands[0] in reg_mapping and operands[1] in reg_mapping:
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arm64_instructions.append(generate_arm64_instruction('asr', [reg_mapping[operands[0]], reg_mapping[operands[1]], handle_immediate('1')]))
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elif x86_ins.mnemonic == 'test':
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operands = parse_operands(x86_ins.op_str)
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if len(operands) == 2 and operands[0] in reg_mapping and operands[1] in reg_mapping:
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arm64_instructions.append(generate_arm64_instruction('tst', [reg_mapping[operands[0]], reg_mapping[operands[1]]]))
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elif x86_ins.mnemonic == 'setcc':
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# Assuming setcc instruction sets flags based on the condition, might be translated to conditional branches
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arm64_instructions.append(f'ccmp {x86_ins.op_str}')
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elif x86_ins.mnemonic == 'cmovcc':
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# Conditional move based on flags, may need conditional branch handling
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arm64_instructions.append(f'csel {x86_ins.op_str}')
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return arm64_instructions
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def main():
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parser = argparse.ArgumentParser(description='Translate x86_64 binary to ARM64 binary')
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parser.add_argument('-i', '--input', required=True, help='Path to the input x86_64 binary file')
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parser.add_argument('-o', '--output', required=True, help='Path to the output ARM64 binary file')
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args = parser.parse_args()
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x86_binary_path = args.input
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arm64_binary_path = args.output
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# Disassemble x86_64 binary
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x86_instructions = disassemble_x86_64(x86_binary_path)
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# Translate x86_64 instructions to ARM64
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arm64_instructions = translate_instructions(x86_instructions)
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# Assemble ARM64 instructions into new binary
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assemble_arm64(arm64_instructions, arm64_binary_path)
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print("Translation complete. ARM64 binary created at", arm64_binary_path)
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if __name__ == "__main__":
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main()
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