Update main.py
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1 changed files with 6 additions and 6 deletions
6
main.py
6
main.py
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@ -16,6 +16,7 @@ def translate_instructions(arm64_instructions):
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for ins in arm64_instructions:
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for ins in arm64_instructions:
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x86_instruction = translate_arm64_to_x86(ins)
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x86_instruction = translate_arm64_to_x86(ins)
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translated_instructions.extend(x86_instruction)
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translated_instructions.extend(x86_instruction)
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print(translated_instructions)
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return translated_instructions
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return translated_instructions
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# Assemble x86_64 instructions into binary
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# Assemble x86_64 instructions into binary
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@ -42,8 +43,7 @@ def translate_arm64_to_x86(arm64_ins):
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# TODO: CLEAN THIS UP
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# TODO: CLEAN THIS UP
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def generate_x86_instruction(opcode, operands):
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def generate_x86_instruction(opcode, operands):
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return f"{opcode} {', '.join(operands)}"
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x86_instructions = []
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if arm64_ins.mnemonic == 'mov':
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if arm64_ins.mnemonic == 'mov':
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operands = arm64_ins.op_str.split(', ')
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operands = arm64_ins.op_str.split(', ')
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if operands[0] in reg_mapping and operands[1] in reg_mapping:
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if operands[0] in reg_mapping and operands[1] in reg_mapping:
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@ -399,7 +399,7 @@ def translate_arm64_to_x86(arm64_ins):
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if operands[0] in reg_mapping and operands[1] in reg_mapping and operands[2] in reg_mapping:
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if operands[0] in reg_mapping and operands[1] in reg_mapping and operands[2] in reg_mapping:
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x86_instructions.append(generate_x86_instruction('mulsd', [reg_mapping[operands[1]], reg_mapping[operands[2]]]))
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x86_instructions.append(generate_x86_instruction('mulsd', [reg_mapping[operands[1]], reg_mapping[operands[2]]]))
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x86_instructions.append(generate_x86_instruction('subsd', [reg_mapping[operands[0]], reg_mapping[operands[1]]]))
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x86_instructions.append(generate_x86_instruction('subsd', [reg_mapping[operands[0]], reg_mapping[operands[1]]]))
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print(x86_instructions)
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return x86_instructions
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return x86_instructions
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def main():
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def main():
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