clean up code/fix improper indents
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parent
6213ed6eba
commit
be9d5bf6ee
1 changed files with 43 additions and 95 deletions
52
main.py
52
main.py
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@ -76,11 +76,6 @@ def translate_arm64_to_x86(arm64_ins):
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if operands[0] in reg_mapping:
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if operands[0] in reg_mapping:
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x86_instructions.append(generate_x86_instruction('mov', [reg_mapping[operands[0]], f"[{operands[1]}]"]))
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x86_instructions.append(generate_x86_instruction('mov', [reg_mapping[operands[0]], f"[{operands[1]}]"]))
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elif arm64_ins.mnemonic == 'stz':
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operands = arm64_ins.op_str.split(', ')
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if operands[1] in reg_mapping:
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x86_instructions.append(generate_x86_instruction('mov', [f"[{operands[0]}]", reg_mapping[operands[1]]]))
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elif 'fma' in arm64_ins.mnemonic and '(63=0)' in arm64_ins.op_str:
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elif 'fma' in arm64_ins.mnemonic and '(63=0)' in arm64_ins.op_str:
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operands = arm64_ins.op_str.split(', ')
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operands = arm64_ins.op_str.split(', ')
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if operands[0] in reg_mapping and operands[1] in reg_mapping:
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if operands[0] in reg_mapping and operands[1] in reg_mapping:
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@ -99,26 +94,6 @@ def translate_arm64_to_x86(arm64_ins):
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x86_instructions.append(generate_x86_instruction('vmulps', [reg_mapping[operands[0]], reg_mapping[operands[0]], reg_mapping[operands[1]]]))
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x86_instructions.append(generate_x86_instruction('vmulps', [reg_mapping[operands[0]], reg_mapping[operands[0]], reg_mapping[operands[1]]]))
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x86_instructions.append(generate_x86_instruction('vaddps', [reg_mapping[operands[0]], reg_mapping[operands[0]], reg_mapping[operands[1]]]))
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x86_instructions.append(generate_x86_instruction('vaddps', [reg_mapping[operands[0]], reg_mapping[operands[0]], reg_mapping[operands[1]]]))
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elif 'vec' in arm64_ins.mnemonic and '(47≠4)' in arm64_ins.op_str:
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operands = arm64_ins.op_str.split(', ')
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if operands[0] in reg_mapping and operands[1] in reg_mapping:
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x86_instructions.append(generate_x86_instruction('vaddps', [reg_mapping[operands[0]], reg_mapping[operands[0]], reg_mapping[operands[1]]]))
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elif 'vec' in arm64_ins.mnemonic and '(47=4)' in arm64_ins.op_str:
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operands = arm64_ins.op_str.split(', ')
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if operands[0] in reg_mapping:
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x86_instructions.append(generate_x86_instruction('vaddps', [reg_mapping[operands[0]], reg_mapping[operands[0]], reg_mapping[operands[0]]]))
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elif arm64_ins.mnemonic == 'extrx':
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operands = arm64_ins.op_str.split(', ')
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if operands[0] in reg_mapping and operands[1] in reg_mapping:
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x86_instructions.append(generate_x86_instruction('mov', [reg_mapping[operands[0]], reg_mapping[operands[1]]]))
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elif arm64_ins.mnemonic == 'extry':
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operands = arm64_ins.op_str.split(', ')
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if operands[0] in reg_mapping and operands[1] in reg_mapping:
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x86_instructions.append(generate_x86_instruction('mov', [reg_mapping[operands[1]], reg_mapping[operands[0]]]))
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elif arm64_ins.mnemonic == 'smulh':
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elif arm64_ins.mnemonic == 'smulh':
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operands = arm64_ins.op_str.split(', ')
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operands = arm64_ins.op_str.split(', ')
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if operands[0] in reg_mapping and operands[1] in reg_mapping:
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if operands[0] in reg_mapping and operands[1] in reg_mapping:
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@ -234,11 +209,6 @@ def translate_arm64_to_x86(arm64_ins):
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if operands[1] in reg_mapping:
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if operands[1] in reg_mapping:
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x86_instructions.append(generate_x86_instruction('mov', [f"[{operands[0]}]", reg_mapping[operands[1]]]))
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x86_instructions.append(generate_x86_instruction('mov', [f"[{operands[0]}]", reg_mapping[operands[1]]]))
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elif arm64_ins.mnemonic == 'stz':
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operands = arm64_ins.op_str.split(', ')
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if operands[1] in reg_mapping:
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x86_instructions.append(generate_x86_instruction('mov', [f"[{operands[0]}]", reg_mapping[operands[1]]]))
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elif 'fma' in arm64_ins.mnemonic and '(63=0)' in arm64_ins.op_str:
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elif 'fma' in arm64_ins.mnemonic and '(63=0)' in arm64_ins.op_str:
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operands = arm64_ins.op_str.split(', ')
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operands = arm64_ins.op_str.split(', ')
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if operands[0] in reg_mapping and operands[1] in reg_mapping:
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if operands[0] in reg_mapping and operands[1] in reg_mapping:
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@ -262,21 +232,6 @@ def translate_arm64_to_x86(arm64_ins):
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if operands[0] in reg_mapping and operands[1] in reg_mapping:
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if operands[0] in reg_mapping and operands[1] in reg_mapping:
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x86_instructions.append(generate_x86_instruction('vaddps', [reg_mapping[operands[0]], reg_mapping[operands[0]], reg_mapping[operands[1]]]))
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x86_instructions.append(generate_x86_instruction('vaddps', [reg_mapping[operands[0]], reg_mapping[operands[0]], reg_mapping[operands[1]]]))
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elif 'vec' in arm64_ins.mnemonic and '(47=4)' in arm64_ins.op_str:
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operands = arm64_ins.op_str.split(', ')
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if operands[0] in reg_mapping:
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x86_instructions.append(generate_x86_instruction('vaddps', [reg_mapping[operands[0]], reg_mapping[operands[0]], reg_mapping[operands[0]]]))
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elif arm64_ins.mnemonic == 'extrx':
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operands = arm64_ins.op_str.split(', ')
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if operands[0] in reg_mapping and operands[1] in reg_mapping:
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x86_instructions.append(generate_x86_instruction('mov', [reg_mapping[operands[0]], reg_mapping[operands[1]]]))
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elif arm64_ins.mnemonic == 'extry':
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operands = arm64_ins.op_str.split(', ')
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if operands[0] in reg_mapping and operands[1] in reg_mapping:
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x86_instructions.append(generate_x86_instruction('mov', [reg_mapping[operands[1]], reg_mapping[operands[0]]]))
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elif arm64_ins.mnemonic == 'umull':
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elif arm64_ins.mnemonic == 'umull':
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if operands[0] in reg_mapping and operands[1] in reg_mapping and operands[2] in reg_mapping and operands[3] in reg_mapping:
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if operands[0] in reg_mapping and operands[1] in reg_mapping and operands[2] in reg_mapping and operands[3] in reg_mapping:
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x86_instructions.append(generate_x86_instruction('mov', [reg_mapping[operands[2]], f"[{reg_mapping[operands[0]]} * {reg_mapping[operands[1]]}]"]))
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x86_instructions.append(generate_x86_instruction('mov', [reg_mapping[operands[2]], f"[{reg_mapping[operands[0]]} * {reg_mapping[operands[1]]}]"]))
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@ -402,13 +357,6 @@ def translate_arm64_to_x86(arm64_ins):
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operands = arm64_ins.op_str.split(', ')
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operands = arm64_ins.op_str.split(', ')
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if operands[0] in reg_mapping and operands[1] in reg_mapping and operands[2] in reg_mapping:
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if operands[0] in reg_mapping and operands[1] in reg_mapping and operands[2] in reg_mapping:
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x86_instructions.append(generate_x86_instruction('divss', [reg_mapping[operands[0]], reg_mapping[operands[1]]]))
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x86_instructions.append(generate_x86_instruction('divss', [reg_mapping[operands[0]], reg_mapping[operands[1]]]))
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elif arm64_ins.mnemonic == 'extrx':
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if operands[0] in reg_mapping and operands[1] in reg_mapping:
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x86_instructions.append(generate_x86_instruction('mov', [reg_mapping[operands[0]], reg_mapping[operands[1]]]))
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elif arm64_ins.mnemonic == 'extry':
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if operands[0] in reg_mapping and operands[1] in reg_mapping:
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x86_instructions.append(generate_x86_instruction('mov', [reg_mapping[operands[0]], reg_mapping[operands[1]]]))
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elif arm64_ins.mnemonic == 'extrh':
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elif arm64_ins.mnemonic == 'extrh':
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if operands[0] in reg_mapping and operands[1] in reg_mapping:
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if operands[0] in reg_mapping and operands[1] in reg_mapping:
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