149 lines
No EOL
4.3 KiB
C
149 lines
No EOL
4.3 KiB
C
#include "pic.h"
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#include "io.h"
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#define PIC1_COMMAND_PORT 0x20
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#define PIC1_DATA_PORT 0x21
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#define PIC2_COMMAND_PORT 0xA0
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#define PIC2_DATA_PORT 0xA1
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// Initialization Control Word 1
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// -----------------------------
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// 0 IC4 if set, the PIC expects to receive ICW4 during initialization
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// 1 SGNL if set, only 1 PIC in the system; if unset, the PIC is cascaded with slave PICs
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// and ICW3 must be sent to controller
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// 2 ADI call address interval, set: 4, not set: 8; ignored on x86, set to 0
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// 3 LTIM if set, operate in level triggered mode; if unset, operate in edge triggered mode
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// 4 INIT set to 1 to initialize PIC
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// 5-7 ignored on x86, set to 0
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enum {
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PIC_ICW1_ICW4 = 0x01,
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PIC_ICW1_SINGLE = 0x02,
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PIC_ICW1_INTERVAL4 = 0x04,
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PIC_ICW1_LEVEL = 0x08,
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PIC_ICW1_INITIALIZE = 0x10
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} PIC_ICW1;
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// Initialization Control Word 4
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// -----------------------------
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// 0 uPM if set, PIC is in 80x86 mode; if cleared, in MCS-80/85 mode
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// 1 AEOI if set, on last interrupt acknowledge pulse, controller automatically performs
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// end of interrupt operation
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// 2 M/S only use if BUF is set; if set, selects buffer master; otherwise, selects buffer slave
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// 3 BUF if set, controller operates in buffered mode
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// 4 SFNM specially fully nested mode; used in systems with large number of cascaded controllers
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// 5-7 reserved, set to 0
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enum {
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PIC_ICW4_8086 = 0x1,
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PIC_ICW4_AUTO_EOI = 0x2,
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PIC_ICW4_BUFFER_MASTER = 0x4,
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PIC_ICW4_BUFFER_SLAVE = 0x0,
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PIC_ICW4_BUFFERRED = 0x8,
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PIC_ICW4_SFNM = 0x10,
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} PIC_ICW4;
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enum {
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PIC_CMD_END_OF_INTERRUPT = 0x20,
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PIC_CMD_READ_IRR = 0x0A,
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PIC_CMD_READ_ISR = 0x0B,
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} PIC_CMD;
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void i686_PIC_Configure(uint8_t offsetPic1, uint8_t offsetPic2)
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{
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// initialization control word 1
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i686_outb(PIC1_COMMAND_PORT, PIC_ICW1_ICW4 | PIC_ICW1_INITIALIZE);
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i686_iowait();
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i686_outb(PIC2_COMMAND_PORT, PIC_ICW1_ICW4 | PIC_ICW1_INITIALIZE);
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i686_iowait();
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// initialization control word 2 - the offsets
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i686_outb(PIC1_DATA_PORT, offsetPic1);
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i686_iowait();
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i686_outb(PIC2_DATA_PORT, offsetPic2);
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i686_iowait();
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// initialization control word 3
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i686_outb(PIC1_DATA_PORT, 0x4); // tell PIC1 that it has a slave at IRQ2 (0000 0100)
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i686_iowait();
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i686_outb(PIC2_DATA_PORT, 0x2); // tell PIC2 its cascade identity (0000 0010)
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i686_iowait();
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// initialization control word 4
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i686_outb(PIC1_DATA_PORT, PIC_ICW4_8086);
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i686_iowait();
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i686_outb(PIC2_DATA_PORT, PIC_ICW4_8086);
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i686_iowait();
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// clear data registers
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i686_outb(PIC1_DATA_PORT, 0);
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i686_iowait();
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i686_outb(PIC2_DATA_PORT, 0);
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i686_iowait();
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}
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void i686_PIC_SendEndOfInterrupt(int irq)
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{
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if (irq >= 8)
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i686_outb(PIC2_COMMAND_PORT, PIC_CMD_END_OF_INTERRUPT);
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i686_outb(PIC1_COMMAND_PORT, PIC_CMD_END_OF_INTERRUPT);
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}
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void i686_PIC_Disable()
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{
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i686_outb(PIC1_DATA_PORT, 0xFF); // mask all
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i686_iowait();
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i686_outb(PIC2_DATA_PORT, 0xFF); // mask all
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i686_iowait();
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}
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void i686_PIC_Mask(int irq)
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{
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uint8_t port;
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if (irq < 8)
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{
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port = PIC1_DATA_PORT;
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}
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else
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{
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irq -= 8;
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port = PIC2_DATA_PORT;
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}
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uint8_t mask = i686_inb(PIC1_DATA_PORT);
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i686_outb(PIC1_DATA_PORT, mask | (1 << irq));
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}
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void i686_PIC_Unmask(int irq)
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{
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uint8_t port;
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if (irq < 8)
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{
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port = PIC1_DATA_PORT;
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}
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else
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{
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irq -= 8;
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port = PIC2_DATA_PORT;
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}
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uint8_t mask = i686_inb(PIC1_DATA_PORT);
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i686_outb(PIC1_DATA_PORT, mask & ~(1 << irq));
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}
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uint16_t i686_PIC_ReadIrqRequestRegister()
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{
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i686_outb(PIC1_COMMAND_PORT, PIC_CMD_READ_IRR);
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i686_outb(PIC2_COMMAND_PORT, PIC_CMD_READ_IRR);
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return ((uint16_t)i686_inb(PIC2_COMMAND_PORT)) | (((uint16_t)i686_inb(PIC2_COMMAND_PORT)) << 8);
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}
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uint16_t i686_PIC_ReadInServiceRegister()
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{
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i686_outb(PIC1_COMMAND_PORT, PIC_CMD_READ_ISR);
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i686_outb(PIC2_COMMAND_PORT, PIC_CMD_READ_ISR);
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return ((uint16_t)i686_inb(PIC2_COMMAND_PORT)) | (((uint16_t)i686_inb(PIC2_COMMAND_PORT)) << 8);
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} |