324 lines
10 KiB
C
324 lines
10 KiB
C
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/*
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* NCR 5380 defines
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*
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* Copyright 1993, Drew Eckhardt
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* Visionary Computing
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* (Unix consulting and custom programming)
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* drew@colorado.edu
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* +1 (303) 666-5836
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*
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* DISTRIBUTION RELEASE 4
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*
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* For more information, please consult
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*
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* NCR 5380 Family
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* SCSI Protocol Controller
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* Databook
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* NCR Microelectronics
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* 1635 Aeroplaza Drive
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* Colorado Springs, CO 80916
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* 1+ (719) 578-3400
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* 1+ (800) 334-5454
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*/
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/*
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* $Log: NCR5380.h,v $
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* Revision 1.3 1994/01/19 05:24:40 drew
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* Added support for TCR LAST_BYTE_SENT bit.
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*
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* Revision 1.3 1994/01/19 05:24:40 drew
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* Added support for TCR LAST_BYTE_SENT bit.
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*
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* Revision 1.2 1994/01/15 06:14:11 drew
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* REAL DMA support, bug fixes.
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*
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* Revision 1.1 1994/01/15 06:00:54 drew
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* Initial revision
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*/
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#ifndef NCR5380_H
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#define NCR5380_H
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#define NCR5380_PUBLIC_RELEASE 4
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#define NDEBUG_ARBITRATION 0x1
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#define NDEBUG_AUTOSENSE 0x2
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#define NDEBUG_DMA 0x4
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#define NDEBUG_HANDSHAKE 0x8
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#define NDEBUG_INFORMATION 0x10
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#define NDEBUG_INIT 0x20
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#define NDEBUG_INTR 0x40
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#define NDEBUG_LINKED 0x80
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#define NDEBUG_MAIN 0x100
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#define NDEBUG_NO_DATAOUT 0x200
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#define NDEBUG_NO_WRITE 0x400
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#define NDEBUG_PIO 0x800
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#define NDEBUG_PSEUDO_DMA 0x1000
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#define NDEBUG_QUEUES 0x2000
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#define NDEBUG_RESELECTION 0x4000
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#define NDEBUG_SELECTION 0x8000
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#define NDEBUG_USLEEP 0x10000
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#define NDEBUG_LAST_BYTE_SENT 0x20000
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/*
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* The contents of the OUTPUT DATA register are asserted on the bus when
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* either arbitration is occuring or the phase-indicating signals (
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* IO, CD, MSG) in the TARGET COMMAND register and the ASSERT DATA
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* bit in the INTITIATOR COMMAND register is set.
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*/
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#define OUTPUT_DATA_REG 0 /* wo DATA lines on SCSI bus */
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#define CURRENT_SCSI_DATA_REG 0 /* ro same */
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#define INITIATOR_COMMAND_REG 1 /* rw */
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#define ICR_ASSERT_RST 0x80 /* rw Set to assert RST */
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#define ICR_ARBITRATION_PROGRESS 0x40 /* ro Indicates arbitration complete */
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#define ICR_TRI_STATE 0x40 /* wo Set to tri-state drivers */
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#define ICR_ARBITRATION_LOST 0x20 /* ro Indicates arbitration lost */
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#define ICR_DIFF_ENABLE 0x20 /* wo Set to enable diff. drivers */
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#define ICR_ASSERT_ACK 0x10 /* rw ini Set to assert ACK */
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#define ICR_ASSERT_BSY 0x08 /* rw Set to assert BSY */
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#define ICR_ASSERT_SEL 0x04 /* rw Set to assert SEL */
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#define ICR_ASSERT_ATN 0x02 /* rw Set to assert ATN */
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#define ICR_ASSERT_DATA 0x01 /* rw SCSI_DATA_REG is asserted */
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#ifdef DIFFERENTIAL
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#define ICR_BASE ICR_DIFF_ENABLE
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#else
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#define ICR_BASE 0
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#endif
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#define MODE_REG 2
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/*
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* Note : BLOCK_DMA code will keep DRQ asserted for the duration of the
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* transfer, causing the chip to hog the bus. You probably don't want
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* this.
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*/
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#define MR_BLOCK_DMA_MODE 0x80 /* rw block mode DMA */
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#define MR_TARGET 0x40 /* rw target mode */
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#define MR_ENABLE_PAR_CHECK 0x20 /* rw enable parity checking */
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#define MR_ENABLE_PAR_INTR 0x10 /* rw enable bad parity interrupt */
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#define MR_ENABLE_EOP_INTR 0x08 /* rw enabble eop interrupt */
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#define MR_MONITOR_BSY 0x04 /* rw enable int on unexpected bsy fail */
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#define MR_DMA_MODE 0x02 /* rw DMA / pseudo DMA mode */
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#define MR_ARBITRATE 0x01 /* rw start arbitration */
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#ifdef PARITY
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#define MR_BASE MR_ENABLE_PAR_CHECK
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#else
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#define MR_BASE 0
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#endif
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#define TARGET_COMMAND_REG 3
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#define TCR_LAST_BYTE_SENT 0x80 /* ro DMA done */
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#define TCR_ASSERT_REQ 0x08 /* tgt rw assert REQ */
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#define TCR_ASSERT_MSG 0x04 /* tgt rw assert MSG */
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#define TCR_ASSERT_CD 0x02 /* tgt rw assert CD */
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#define TCR_ASSERT_IO 0x01 /* tgt rw assert IO */
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#define STATUS_REG 4 /* ro */
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/*
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* Note : a set bit indicates an active signal, driven by us or another
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* device.
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*/
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#define SR_RST 0x80
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#define SR_BSY 0x40
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#define SR_REQ 0x20
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#define SR_MSG 0x10
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#define SR_CD 0x08
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#define SR_IO 0x04
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#define SR_SEL 0x02
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#define SR_DBP 0x01
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/*
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* Setting a bit in this register will cause an interrupt to be generated when
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* BSY is false and SEL true and this bit is asserted on the bus.
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*/
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#define SELECT_ENABLE_REG 4 /* wo */
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#define BUS_AND_STATUS_REG 5 /* ro */
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#define BASR_END_DMA_TRANSFER 0x80 /* ro set on end of transfer */
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#define BASR_DRQ 0x40 /* ro mirror of DRQ pin */
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#define BASR_PARITY_ERROR 0x20 /* ro parity error detected */
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#define BASR_IRQ 0x10 /* ro mirror of IRQ pin */
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#define BASR_PHASE_MATCH 0x08 /* ro Set when MSG CD IO match TCR */
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#define BASR_BUSY_ERROR 0x04 /* ro Unexpected change to inactive state */
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#define BASR_ATN 0x02 /* ro BUS status */
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#define BASR_ACK 0x01 /* ro BUS status */
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/* Write any value to this register to start a DMA send */
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#define START_DMA_SEND_REG 5 /* wo */
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/*
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* Used in DMA transfer mode, data is latched from the SCSI bus on
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* the falling edge of REQ (ini) or ACK (tgt)
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*/
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#define INPUT_DATA_REG 6 /* ro */
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/* Write any value to this register to start a DMA recieve */
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#define START_DMA_TARGET_RECIEVE_REG 6 /* wo */
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/* Read this register to clear interrupt conditions */
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#define RESET_PARITY_INTERRUPT_REG 7 /* ro */
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/* Write any value to this register to start an ini mode DMA recieve */
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#define START_DMA_INITIATOR_RECIEVE_REG 7 /* wo */
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/* Note : PHASE_* macros are based on the values of the STATUS register */
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#define PHASE_MASK (SR_MSG | SR_CD | SR_IO)
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#define PHASE_DATAOUT 0
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#define PHASE_DATAIN SR_IO
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#define PHASE_CMDOUT SR_CD
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#define PHASE_STATIN (SR_CD | SR_IO)
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#define PHASE_MSGOUT (SR_MSG | SR_CD)
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#define PHASE_MSGIN (SR_MSG | SR_CD | SR_IO)
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#define PHASE_UNKNOWN 0xff
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/*
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* Convert status register phase to something we can use to set phase in
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* the target register so we can get phase mismatch interrupts on DMA
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* transfers.
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*/
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#define PHASE_SR_TO_TCR(phase) ((phase) >> 2)
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/*
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* The internal should_disconnect() function returns these based on the
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* expected length of a disconnect if a device supports disconnect/
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* reconnect.
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*/
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#define DISCONNECT_NONE 0
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#define DISCONNECT_TIME_TO_DATA 1
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#define DISCONNECT_LONG 2
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/*
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* These are "special" values for the tag parameter passed to NCR5380_select.
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*/
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#define TAG_NEXT -1 /* Use next free tag */
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#define TAG_NONE -2 /*
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* Establish I_T_L nexus instead of I_T_L_Q
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* even on SCSI-II devices.
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*/
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/*
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* These are "special" values for the irq and dma_channel fields of the
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* Scsi_Host structure
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*/
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#define IRQ_NONE 255
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#define DMA_NONE 255
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#define IRQ_AUTO 254
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#define DMA_AUTO 254
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#define FLAG_HAS_LAST_BYTE_SENT 1 /* NCR53c81 or better */
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#define FLAG_CHECK_LAST_BYTE_SENT 2 /* Only test once */
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#ifndef ASM
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struct NCR5380_hostdata {
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NCR5380_implementation_fields; /* implmenentation specific */
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unsigned char id_mask, id_higher_mask; /* 1 << id, all bits greater */
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volatile unsigned char busy[8]; /* index = target, bit = lun */
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#if defined(REAL_DMA) || defined(REAL_DMA_POLL)
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volatile int dma_len; /* requested length of DMA */
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#endif
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volatile unsigned char last_message; /* last message OUT */
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volatile Scsi_Cmnd *connected; /* currently connected command */
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volatile Scsi_Cmnd *issue_queue; /* waiting to be issued */
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volatile Scsi_Cmnd *disconnected_queue; /* waiting for reconnect */
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int flags;
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#ifdef USLEEP
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unsigned long time_expires; /* in jiffies, set prior to sleeping */
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struct Scsi_Host *next_timer;
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#endif
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};
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#ifdef __KERNEL__
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static struct Scsi_Host *first_instance; /* linked list of 5380's */
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#if defined(AUTOPROBE_IRQ)
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static int NCR5380_probe_irq (struct Scsi_Host *instance, int possible);
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#endif
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static void NCR5380_init (struct Scsi_Host *instance);
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static void NCR5380_information_transfer (struct Scsi_Host *instance);
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static void NCR5380_intr (int irq);
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static void NCR5380_main (void);
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static void NCR5380_print_options (struct Scsi_Host *instance);
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#ifndef NCR5380_abort
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static
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#endif
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int NCR5380_abort (Scsi_Cmnd *cmd, int code);
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#ifndef NCR5380_reset
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static
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#endif
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int NCR5380_reset (Scsi_Cmnd *cmd);
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#ifndef NCR5380_queue_command
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static
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#endif
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int NCR5380_queue_command (Scsi_Cmnd *cmd, void (*done)(Scsi_Cmnd *));
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static void NCR5380_reselect (struct Scsi_Host *instance);
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static int NCR5380_select (struct Scsi_Host *instance, Scsi_Cmnd *cmd, int tag);
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#if defined(PSEUDO_DMA) || defined(REAL_DMA) || defined(REAL_DMA_POLL)
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static int NCR5380_transfer_dma (struct Scsi_Host *instance,
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unsigned char *phase, int *count, unsigned char **data);
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#endif
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static int NCR5380_transfer_pio (struct Scsi_Host *instance,
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unsigned char *phase, int *count, unsigned char **data);
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#if (defined(REAL_DMA) || defined(REAL_DMA_POLL)) && defined(i386)
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static __inline__ int NCR5380_i386_dma_setup (struct Scsi_Host *instance,
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unsigned char *ptr, unsigned int count, unsigned char mode) {
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unsigned limit;
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if (instance->dma_channel <=3) {
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if (count > 65536)
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count = 65536;
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limit = 65536 - (((unsigned) ptr) & 0xFFFF);
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} else {
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if (count > 65536 * 2)
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count = 65536 * 2;
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limit = 65536* 2 - (((unsigned) ptr) & 0x1FFFF);
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}
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if (count > limit) count = limit;
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if ((count & 1) || (((unsigned) ptr) & 1))
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panic ("scsi%d : attmpted unaligned DMA transfer\n", instance->host_no);
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cli();
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disable_dma(instance->dma_channel);
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clear_dma_ff(instance->dma_channel);
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set_dma_addr(instance->dma_channel, (unsigned int) ptr);
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set_dma_count(instance->dma_channel, count);
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set_dma_mode(instance->dma_channel, mode);
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enable_dma(instance->dma_channel);
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sti();
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return count;
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}
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static __inline__ int NCR5380_i386_dma_write_setup (struct Scsi_Host *instance,
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unsigned char *src, unsigned int count) {
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return NCR5380_i386_dma_setup (instance, src, count, DMA_MODE_WRITE);
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}
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static __inline__ int NCR5380_i386_dma_read_setup (struct Scsi_Host *instance,
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unsigned char *src, unsigned int count) {
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return NCR5380_i386_dma_setup (instance, src, count, DMA_MODE_READ);
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}
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static __inline__ int NCR5380_i386_dma_residual (struct Scsi_Host *instance) {
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register int tmp;
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cli();
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clear_dma_ff(instance->dma_channel);
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tmp = get_dma_residue(instance->dma_channel);
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sti();
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return tmp;
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}
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#endif /* defined(REAL_DMA) && defined(i386) */
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#endif __KERNEL_
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#endif /* ndef ASM */
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#endif /* NCR5380_H */
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