321 lines
8.8 KiB
C
321 lines
8.8 KiB
C
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/*
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* AVR USART
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*
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* Copyright (c) 2018 University of Kent
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* Author: Sarah Harris
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#include "qemu/osdep.h"
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#include "hw/char/avr_usart.h"
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#include "qemu/log.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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static int avr_usart_can_receive(void *opaque)
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{
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AVRUsartState *usart = opaque;
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if (usart->data_valid || !(usart->csrb & USART_CSRB_RXEN)) {
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return 0;
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}
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return 1;
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}
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static void avr_usart_receive(void *opaque, const uint8_t *buffer, int size)
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{
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AVRUsartState *usart = opaque;
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assert(size == 1);
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assert(!usart->data_valid);
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usart->data = buffer[0];
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usart->data_valid = true;
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usart->csra |= USART_CSRA_RXC;
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if (usart->csrb & USART_CSRB_RXCIE) {
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qemu_set_irq(usart->rxc_irq, 1);
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}
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}
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static void update_char_mask(AVRUsartState *usart)
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{
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uint8_t mode = ((usart->csrc & USART_CSRC_CSZ0) ? 1 : 0) |
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((usart->csrc & USART_CSRC_CSZ1) ? 2 : 0) |
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((usart->csrb & USART_CSRB_CSZ2) ? 4 : 0);
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switch (mode) {
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case 0:
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usart->char_mask = 0b11111;
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break;
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case 1:
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usart->char_mask = 0b111111;
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break;
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case 2:
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usart->char_mask = 0b1111111;
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break;
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case 3:
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usart->char_mask = 0b11111111;
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break;
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case 4:
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/* Fallthrough. */
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case 5:
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/* Fallthrough. */
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case 6:
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qemu_log_mask(
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LOG_GUEST_ERROR,
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"%s: Reserved character size 0x%x\n",
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__func__,
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mode);
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break;
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case 7:
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qemu_log_mask(
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LOG_GUEST_ERROR,
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"%s: Nine bit character size not supported (forcing eight)\n",
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__func__);
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usart->char_mask = 0b11111111;
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break;
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default:
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assert(0);
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}
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}
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static void avr_usart_reset(DeviceState *dev)
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{
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AVRUsartState *usart = AVR_USART(dev);
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usart->data_valid = false;
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usart->csra = 0b00100000;
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usart->csrb = 0b00000000;
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usart->csrc = 0b00000110;
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usart->brrl = 0;
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usart->brrh = 0;
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update_char_mask(usart);
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qemu_set_irq(usart->rxc_irq, 0);
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qemu_set_irq(usart->txc_irq, 0);
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qemu_set_irq(usart->dre_irq, 0);
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}
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static uint64_t avr_usart_read(void *opaque, hwaddr addr, unsigned int size)
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{
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AVRUsartState *usart = opaque;
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uint8_t data;
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assert(size == 1);
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if (!usart->enabled) {
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return 0;
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}
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switch (addr) {
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case USART_DR:
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if (!(usart->csrb & USART_CSRB_RXEN)) {
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/* Receiver disabled, ignore. */
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return 0;
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}
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if (usart->data_valid) {
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data = usart->data & usart->char_mask;
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usart->data_valid = false;
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} else {
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data = 0;
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}
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usart->csra &= 0xff ^ USART_CSRA_RXC;
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qemu_set_irq(usart->rxc_irq, 0);
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qemu_chr_fe_accept_input(&usart->chr);
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return data;
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case USART_CSRA:
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return usart->csra;
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case USART_CSRB:
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return usart->csrb;
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case USART_CSRC:
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return usart->csrc;
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case USART_BRRL:
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return usart->brrl;
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case USART_BRRH:
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return usart->brrh;
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default:
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qemu_log_mask(
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LOG_GUEST_ERROR,
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"%s: Bad offset 0x%"HWADDR_PRIx"\n",
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__func__,
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addr);
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}
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return 0;
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}
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static void avr_usart_write(void *opaque, hwaddr addr, uint64_t value,
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unsigned int size)
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{
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AVRUsartState *usart = opaque;
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uint8_t mask;
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uint8_t data;
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assert((value & 0xff) == value);
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assert(size == 1);
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if (!usart->enabled) {
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return;
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}
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switch (addr) {
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case USART_DR:
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if (!(usart->csrb & USART_CSRB_TXEN)) {
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/* Transmitter disabled, ignore. */
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return;
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}
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usart->csra |= USART_CSRA_TXC;
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usart->csra |= USART_CSRA_DRE;
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if (usart->csrb & USART_CSRB_TXCIE) {
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qemu_set_irq(usart->txc_irq, 1);
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usart->csra &= 0xff ^ USART_CSRA_TXC;
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}
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if (usart->csrb & USART_CSRB_DREIE) {
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qemu_set_irq(usart->dre_irq, 1);
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}
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data = value;
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qemu_chr_fe_write_all(&usart->chr, &data, 1);
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break;
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case USART_CSRA:
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mask = 0b01000011;
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/* Mask read-only bits. */
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value = (value & mask) | (usart->csra & (0xff ^ mask));
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usart->csra = value;
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if (value & USART_CSRA_TXC) {
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usart->csra ^= USART_CSRA_TXC;
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qemu_set_irq(usart->txc_irq, 0);
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}
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if (value & USART_CSRA_MPCM) {
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qemu_log_mask(
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LOG_GUEST_ERROR,
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"%s: MPCM not supported by USART\n",
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__func__);
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}
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break;
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case USART_CSRB:
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mask = 0b11111101;
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/* Mask read-only bits. */
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value = (value & mask) | (usart->csrb & (0xff ^ mask));
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usart->csrb = value;
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if (!(value & USART_CSRB_RXEN)) {
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/* Receiver disabled, flush input buffer. */
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usart->data_valid = false;
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}
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qemu_set_irq(usart->rxc_irq,
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((value & USART_CSRB_RXCIE) &&
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(usart->csra & USART_CSRA_RXC)) ? 1 : 0);
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qemu_set_irq(usart->txc_irq,
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((value & USART_CSRB_TXCIE) &&
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(usart->csra & USART_CSRA_TXC)) ? 1 : 0);
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qemu_set_irq(usart->dre_irq,
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((value & USART_CSRB_DREIE) &&
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(usart->csra & USART_CSRA_DRE)) ? 1 : 0);
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update_char_mask(usart);
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break;
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case USART_CSRC:
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usart->csrc = value;
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if ((value & USART_CSRC_MSEL1) && (value & USART_CSRC_MSEL0)) {
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qemu_log_mask(
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LOG_GUEST_ERROR,
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"%s: SPI mode not supported by USART\n",
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__func__);
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}
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if ((value & USART_CSRC_MSEL1) && !(value & USART_CSRC_MSEL0)) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad USART mode\n", __func__);
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}
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if (!(value & USART_CSRC_PM1) && (value & USART_CSRC_PM0)) {
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qemu_log_mask(
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LOG_GUEST_ERROR,
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"%s: Bad USART parity mode\n",
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__func__);
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}
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update_char_mask(usart);
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break;
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case USART_BRRL:
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usart->brrl = value;
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break;
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case USART_BRRH:
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usart->brrh = value & 0b00001111;
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break;
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default:
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qemu_log_mask(
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LOG_GUEST_ERROR,
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"%s: Bad offset 0x%"HWADDR_PRIx"\n",
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__func__,
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addr);
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}
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}
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static const MemoryRegionOps avr_usart_ops = {
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.read = avr_usart_read,
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.write = avr_usart_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.impl = {.min_access_size = 1, .max_access_size = 1}
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};
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static Property avr_usart_properties[] = {
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DEFINE_PROP_CHR("chardev", AVRUsartState, chr),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void avr_usart_pr(void *opaque, int irq, int level)
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{
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AVRUsartState *s = AVR_USART(opaque);
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s->enabled = !level;
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if (!s->enabled) {
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avr_usart_reset(DEVICE(s));
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}
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}
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static void avr_usart_init(Object *obj)
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{
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AVRUsartState *s = AVR_USART(obj);
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sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->rxc_irq);
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sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->dre_irq);
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sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->txc_irq);
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memory_region_init_io(&s->mmio, obj, &avr_usart_ops, s, TYPE_AVR_USART, 7);
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sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
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qdev_init_gpio_in(DEVICE(s), avr_usart_pr, 1);
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s->enabled = true;
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}
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static void avr_usart_realize(DeviceState *dev, Error **errp)
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{
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AVRUsartState *s = AVR_USART(dev);
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qemu_chr_fe_set_handlers(&s->chr, avr_usart_can_receive,
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avr_usart_receive, NULL, NULL,
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s, NULL, true);
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avr_usart_reset(dev);
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}
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static void avr_usart_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = avr_usart_reset;
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device_class_set_props(dc, avr_usart_properties);
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dc->realize = avr_usart_realize;
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}
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static const TypeInfo avr_usart_info = {
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.name = TYPE_AVR_USART,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(AVRUsartState),
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.instance_init = avr_usart_init,
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.class_init = avr_usart_class_init,
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};
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static void avr_usart_register_types(void)
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{
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type_register_static(&avr_usart_info);
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}
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type_init(avr_usart_register_types)
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