411 lines
12 KiB
C
411 lines
12 KiB
C
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/*
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* Raspberry Pi emulation (c) 2012 Gregory Estrade
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "hw/dma/bcm2835_dma.h"
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#include "hw/irq.h"
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#include "migration/vmstate.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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/* DMA CS Control and Status bits */
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#define BCM2708_DMA_ACTIVE (1 << 0)
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#define BCM2708_DMA_END (1 << 1) /* GE */
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#define BCM2708_DMA_INT (1 << 2)
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#define BCM2708_DMA_ISPAUSED (1 << 4) /* Pause requested or not active */
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#define BCM2708_DMA_ISHELD (1 << 5) /* Is held by DREQ flow control */
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#define BCM2708_DMA_ERR (1 << 8)
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#define BCM2708_DMA_ABORT (1 << 30) /* stop current CB, go to next, WO */
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#define BCM2708_DMA_RESET (1 << 31) /* WO, self clearing */
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/* DMA control block "info" field bits */
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#define BCM2708_DMA_INT_EN (1 << 0)
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#define BCM2708_DMA_TDMODE (1 << 1)
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#define BCM2708_DMA_WAIT_RESP (1 << 3)
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#define BCM2708_DMA_D_INC (1 << 4)
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#define BCM2708_DMA_D_WIDTH (1 << 5)
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#define BCM2708_DMA_D_DREQ (1 << 6)
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#define BCM2708_DMA_D_IGNORE (1 << 7)
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#define BCM2708_DMA_S_INC (1 << 8)
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#define BCM2708_DMA_S_WIDTH (1 << 9)
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#define BCM2708_DMA_S_DREQ (1 << 10)
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#define BCM2708_DMA_S_IGNORE (1 << 11)
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/* Register offsets */
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#define BCM2708_DMA_CS 0x00 /* Control and Status */
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#define BCM2708_DMA_ADDR 0x04 /* Control block address */
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/* the current control block appears in the following registers - read only */
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#define BCM2708_DMA_INFO 0x08
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#define BCM2708_DMA_SOURCE_AD 0x0c
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#define BCM2708_DMA_DEST_AD 0x10
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#define BCM2708_DMA_TXFR_LEN 0x14
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#define BCM2708_DMA_STRIDE 0x18
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#define BCM2708_DMA_NEXTCB 0x1C
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#define BCM2708_DMA_DEBUG 0x20
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#define BCM2708_DMA_INT_STATUS 0xfe0 /* Interrupt status of each channel */
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#define BCM2708_DMA_ENABLE 0xff0 /* Global enable bits for each channel */
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#define BCM2708_DMA_CS_RW_MASK 0x30ff0001 /* All RW bits in DMA_CS */
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static void bcm2835_dma_update(BCM2835DMAState *s, unsigned c)
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{
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BCM2835DMAChan *ch = &s->chan[c];
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uint32_t data, xlen, xlen_td, ylen;
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int16_t dst_stride, src_stride;
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if (!(s->enable & (1 << c))) {
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return;
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}
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while ((s->enable & (1 << c)) && (ch->conblk_ad != 0)) {
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/* CB fetch */
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ch->ti = ldl_le_phys(&s->dma_as, ch->conblk_ad);
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ch->source_ad = ldl_le_phys(&s->dma_as, ch->conblk_ad + 4);
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ch->dest_ad = ldl_le_phys(&s->dma_as, ch->conblk_ad + 8);
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ch->txfr_len = ldl_le_phys(&s->dma_as, ch->conblk_ad + 12);
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ch->stride = ldl_le_phys(&s->dma_as, ch->conblk_ad + 16);
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ch->nextconbk = ldl_le_phys(&s->dma_as, ch->conblk_ad + 20);
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ylen = 1;
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if (ch->ti & BCM2708_DMA_TDMODE) {
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/* 2D transfer mode */
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ylen += (ch->txfr_len >> 16) & 0x3fff;
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xlen = ch->txfr_len & 0xffff;
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dst_stride = ch->stride >> 16;
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src_stride = ch->stride & 0xffff;
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} else {
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xlen = ch->txfr_len;
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dst_stride = 0;
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src_stride = 0;
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}
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xlen_td = xlen;
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while (ylen != 0) {
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/* Normal transfer mode */
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while (xlen != 0) {
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if (ch->ti & BCM2708_DMA_S_IGNORE) {
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/* Ignore reads */
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data = 0;
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} else {
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data = ldl_le_phys(&s->dma_as, ch->source_ad);
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}
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if (ch->ti & BCM2708_DMA_S_INC) {
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ch->source_ad += 4;
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}
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if (ch->ti & BCM2708_DMA_D_IGNORE) {
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/* Ignore writes */
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} else {
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stl_le_phys(&s->dma_as, ch->dest_ad, data);
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}
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if (ch->ti & BCM2708_DMA_D_INC) {
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ch->dest_ad += 4;
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}
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/* update remaining transfer length */
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xlen -= 4;
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if (ch->ti & BCM2708_DMA_TDMODE) {
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ch->txfr_len = (ylen << 16) | xlen;
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} else {
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ch->txfr_len = xlen;
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}
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}
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if (--ylen != 0) {
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ch->source_ad += src_stride;
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ch->dest_ad += dst_stride;
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xlen = xlen_td;
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}
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}
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ch->cs |= BCM2708_DMA_END;
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if (ch->ti & BCM2708_DMA_INT_EN) {
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ch->cs |= BCM2708_DMA_INT;
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s->int_status |= (1 << c);
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qemu_set_irq(ch->irq, 1);
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}
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/* Process next CB */
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ch->conblk_ad = ch->nextconbk;
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}
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ch->cs &= ~BCM2708_DMA_ACTIVE;
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ch->cs |= BCM2708_DMA_ISPAUSED;
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}
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static void bcm2835_dma_chan_reset(BCM2835DMAChan *ch)
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{
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ch->cs = 0;
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ch->conblk_ad = 0;
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}
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static uint64_t bcm2835_dma_read(BCM2835DMAState *s, hwaddr offset,
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unsigned size, unsigned c)
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{
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BCM2835DMAChan *ch;
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uint32_t res = 0;
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assert(size == 4);
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assert(c < BCM2835_DMA_NCHANS);
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ch = &s->chan[c];
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switch (offset) {
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case BCM2708_DMA_CS:
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res = ch->cs;
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break;
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case BCM2708_DMA_ADDR:
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res = ch->conblk_ad;
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break;
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case BCM2708_DMA_INFO:
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res = ch->ti;
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break;
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case BCM2708_DMA_SOURCE_AD:
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res = ch->source_ad;
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break;
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case BCM2708_DMA_DEST_AD:
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res = ch->dest_ad;
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break;
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case BCM2708_DMA_TXFR_LEN:
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res = ch->txfr_len;
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break;
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case BCM2708_DMA_STRIDE:
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res = ch->stride;
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break;
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case BCM2708_DMA_NEXTCB:
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res = ch->nextconbk;
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break;
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case BCM2708_DMA_DEBUG:
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res = ch->debug;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"HWADDR_PRIx"\n",
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__func__, offset);
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break;
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}
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return res;
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}
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static void bcm2835_dma_write(BCM2835DMAState *s, hwaddr offset,
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uint64_t value, unsigned size, unsigned c)
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{
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BCM2835DMAChan *ch;
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uint32_t oldcs;
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assert(size == 4);
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assert(c < BCM2835_DMA_NCHANS);
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ch = &s->chan[c];
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switch (offset) {
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case BCM2708_DMA_CS:
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oldcs = ch->cs;
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if (value & BCM2708_DMA_RESET) {
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bcm2835_dma_chan_reset(ch);
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}
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if (value & BCM2708_DMA_ABORT) {
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/* abort is a no-op, since we always run to completion */
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}
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if (value & BCM2708_DMA_END) {
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ch->cs &= ~BCM2708_DMA_END;
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}
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if (value & BCM2708_DMA_INT) {
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ch->cs &= ~BCM2708_DMA_INT;
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s->int_status &= ~(1 << c);
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qemu_set_irq(ch->irq, 0);
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}
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ch->cs &= ~BCM2708_DMA_CS_RW_MASK;
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ch->cs |= (value & BCM2708_DMA_CS_RW_MASK);
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if (!(oldcs & BCM2708_DMA_ACTIVE) && (ch->cs & BCM2708_DMA_ACTIVE)) {
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bcm2835_dma_update(s, c);
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}
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break;
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case BCM2708_DMA_ADDR:
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ch->conblk_ad = value;
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break;
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case BCM2708_DMA_DEBUG:
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ch->debug = value;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"HWADDR_PRIx"\n",
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__func__, offset);
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break;
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}
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}
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static uint64_t bcm2835_dma0_read(void *opaque, hwaddr offset, unsigned size)
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{
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BCM2835DMAState *s = opaque;
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if (offset < 0xf00) {
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return bcm2835_dma_read(s, (offset & 0xff), size, (offset >> 8) & 0xf);
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} else {
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switch (offset) {
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case BCM2708_DMA_INT_STATUS:
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return s->int_status;
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case BCM2708_DMA_ENABLE:
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return s->enable;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"HWADDR_PRIx"\n",
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__func__, offset);
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return 0;
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}
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}
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}
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static uint64_t bcm2835_dma15_read(void *opaque, hwaddr offset, unsigned size)
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{
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return bcm2835_dma_read(opaque, (offset & 0xff), size, 15);
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}
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static void bcm2835_dma0_write(void *opaque, hwaddr offset, uint64_t value,
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unsigned size)
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{
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BCM2835DMAState *s = opaque;
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if (offset < 0xf00) {
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bcm2835_dma_write(s, (offset & 0xff), value, size, (offset >> 8) & 0xf);
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} else {
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switch (offset) {
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case BCM2708_DMA_INT_STATUS:
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break;
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case BCM2708_DMA_ENABLE:
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s->enable = (value & 0xffff);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"HWADDR_PRIx"\n",
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__func__, offset);
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}
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}
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}
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static void bcm2835_dma15_write(void *opaque, hwaddr offset, uint64_t value,
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unsigned size)
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{
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bcm2835_dma_write(opaque, (offset & 0xff), value, size, 15);
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}
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static const MemoryRegionOps bcm2835_dma0_ops = {
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.read = bcm2835_dma0_read,
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.write = bcm2835_dma0_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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};
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static const MemoryRegionOps bcm2835_dma15_ops = {
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.read = bcm2835_dma15_read,
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.write = bcm2835_dma15_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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};
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static const VMStateDescription vmstate_bcm2835_dma_chan = {
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.name = TYPE_BCM2835_DMA "-chan",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(cs, BCM2835DMAChan),
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VMSTATE_UINT32(conblk_ad, BCM2835DMAChan),
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VMSTATE_UINT32(ti, BCM2835DMAChan),
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VMSTATE_UINT32(source_ad, BCM2835DMAChan),
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VMSTATE_UINT32(dest_ad, BCM2835DMAChan),
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VMSTATE_UINT32(txfr_len, BCM2835DMAChan),
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VMSTATE_UINT32(stride, BCM2835DMAChan),
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VMSTATE_UINT32(nextconbk, BCM2835DMAChan),
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VMSTATE_UINT32(debug, BCM2835DMAChan),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_bcm2835_dma = {
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.name = TYPE_BCM2835_DMA,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_STRUCT_ARRAY(chan, BCM2835DMAState, BCM2835_DMA_NCHANS, 1,
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vmstate_bcm2835_dma_chan, BCM2835DMAChan),
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VMSTATE_UINT32(int_status, BCM2835DMAState),
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VMSTATE_UINT32(enable, BCM2835DMAState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void bcm2835_dma_init(Object *obj)
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{
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BCM2835DMAState *s = BCM2835_DMA(obj);
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int n;
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/* DMA channels 0-14 occupy a contiguous block of IO memory, along
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* with the global enable and interrupt status bits. Channel 15
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* has the same register map, but is mapped at a discontiguous
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* address in a separate IO block.
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*/
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memory_region_init_io(&s->iomem0, OBJECT(s), &bcm2835_dma0_ops, s,
|
||
|
|
TYPE_BCM2835_DMA, 0x1000);
|
||
|
|
sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem0);
|
||
|
|
|
||
|
|
memory_region_init_io(&s->iomem15, OBJECT(s), &bcm2835_dma15_ops, s,
|
||
|
|
TYPE_BCM2835_DMA "-chan15", 0x100);
|
||
|
|
sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem15);
|
||
|
|
|
||
|
|
for (n = 0; n < 16; n++) {
|
||
|
|
sysbus_init_irq(SYS_BUS_DEVICE(s), &s->chan[n].irq);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static void bcm2835_dma_reset(DeviceState *dev)
|
||
|
|
{
|
||
|
|
BCM2835DMAState *s = BCM2835_DMA(dev);
|
||
|
|
int n;
|
||
|
|
|
||
|
|
s->enable = 0xffff;
|
||
|
|
s->int_status = 0;
|
||
|
|
for (n = 0; n < BCM2835_DMA_NCHANS; n++) {
|
||
|
|
bcm2835_dma_chan_reset(&s->chan[n]);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static void bcm2835_dma_realize(DeviceState *dev, Error **errp)
|
||
|
|
{
|
||
|
|
BCM2835DMAState *s = BCM2835_DMA(dev);
|
||
|
|
Object *obj;
|
||
|
|
|
||
|
|
obj = object_property_get_link(OBJECT(dev), "dma-mr", &error_abort);
|
||
|
|
s->dma_mr = MEMORY_REGION(obj);
|
||
|
|
address_space_init(&s->dma_as, s->dma_mr, TYPE_BCM2835_DMA "-memory");
|
||
|
|
|
||
|
|
bcm2835_dma_reset(dev);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void bcm2835_dma_class_init(ObjectClass *klass, void *data)
|
||
|
|
{
|
||
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
||
|
|
|
||
|
|
dc->realize = bcm2835_dma_realize;
|
||
|
|
dc->reset = bcm2835_dma_reset;
|
||
|
|
dc->vmsd = &vmstate_bcm2835_dma;
|
||
|
|
}
|
||
|
|
|
||
|
|
static TypeInfo bcm2835_dma_info = {
|
||
|
|
.name = TYPE_BCM2835_DMA,
|
||
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
||
|
|
.instance_size = sizeof(BCM2835DMAState),
|
||
|
|
.class_init = bcm2835_dma_class_init,
|
||
|
|
.instance_init = bcm2835_dma_init,
|
||
|
|
};
|
||
|
|
|
||
|
|
static void bcm2835_dma_register_types(void)
|
||
|
|
{
|
||
|
|
type_register_static(&bcm2835_dma_info);
|
||
|
|
}
|
||
|
|
|
||
|
|
type_init(bcm2835_dma_register_types)
|