611 lines
18 KiB
C
611 lines
18 KiB
C
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/*
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* HP-PARISC Dino PCI chipset emulation, as in B160L and similiar machines
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*
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* (C) 2017-2019 by Helge Deller <deller@gmx.de>
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*
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* This work is licensed under the GNU GPL license version 2 or later.
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*
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* Documentation available at:
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* https://parisc.wiki.kernel.org/images-parisc/9/91/Dino_ers.pdf
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* https://parisc.wiki.kernel.org/images-parisc/7/70/Dino_3_1_Errata.pdf
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*/
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#include "qemu/osdep.h"
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#include "qemu/module.h"
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#include "qemu/units.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "hw/irq.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_bus.h"
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#include "migration/vmstate.h"
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#include "hppa_sys.h"
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#include "exec/address-spaces.h"
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#include "trace.h"
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#define TYPE_DINO_PCI_HOST_BRIDGE "dino-pcihost"
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#define DINO_IAR0 0x004
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#define DINO_IODC 0x008
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#define DINO_IRR0 0x00C /* RO */
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#define DINO_IAR1 0x010
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#define DINO_IRR1 0x014 /* RO */
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#define DINO_IMR 0x018
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#define DINO_IPR 0x01C
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#define DINO_TOC_ADDR 0x020
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#define DINO_ICR 0x024
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#define DINO_ILR 0x028 /* RO */
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#define DINO_IO_COMMAND 0x030 /* WO */
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#define DINO_IO_STATUS 0x034 /* RO */
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#define DINO_IO_CONTROL 0x038
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#define DINO_IO_GSC_ERR_RESP 0x040 /* RO */
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#define DINO_IO_ERR_INFO 0x044 /* RO */
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#define DINO_IO_PCI_ERR_RESP 0x048 /* RO */
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#define DINO_IO_FBB_EN 0x05c
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#define DINO_IO_ADDR_EN 0x060
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#define DINO_PCI_CONFIG_ADDR 0x064
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#define DINO_PCI_CONFIG_DATA 0x068
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#define DINO_PCI_IO_DATA 0x06c
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#define DINO_PCI_MEM_DATA 0x070 /* Dino 3.x only */
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#define DINO_GSC2X_CONFIG 0x7b4 /* RO */
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#define DINO_GMASK 0x800
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#define DINO_PAMR 0x804
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#define DINO_PAPR 0x808
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#define DINO_DAMODE 0x80c
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#define DINO_PCICMD 0x810
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#define DINO_PCISTS 0x814 /* R/WC */
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#define DINO_MLTIM 0x81c
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#define DINO_BRDG_FEAT 0x820
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#define DINO_PCIROR 0x824
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#define DINO_PCIWOR 0x828
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#define DINO_TLTIM 0x830
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#define DINO_IRQS 11 /* bits 0-10 are architected */
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#define DINO_IRR_MASK 0x5ff /* only 10 bits are implemented */
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#define DINO_LOCAL_IRQS (DINO_IRQS + 1)
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#define DINO_MASK_IRQ(x) (1 << (x))
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#define PCIINTA 0x001
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#define PCIINTB 0x002
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#define PCIINTC 0x004
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#define PCIINTD 0x008
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#define PCIINTE 0x010
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#define PCIINTF 0x020
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#define GSCEXTINT 0x040
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/* #define xxx 0x080 - bit 7 is "default" */
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/* #define xxx 0x100 - bit 8 not used */
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/* #define xxx 0x200 - bit 9 not used */
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#define RS232INT 0x400
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#define DINO_MEM_CHUNK_SIZE (8 * MiB)
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#define DINO_PCI_HOST_BRIDGE(obj) \
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OBJECT_CHECK(DinoState, (obj), TYPE_DINO_PCI_HOST_BRIDGE)
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#define DINO800_REGS (1 + (DINO_TLTIM - DINO_GMASK) / 4)
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static const uint32_t reg800_keep_bits[DINO800_REGS] = {
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MAKE_64BIT_MASK(0, 1), /* GMASK */
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MAKE_64BIT_MASK(0, 7), /* PAMR */
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MAKE_64BIT_MASK(0, 7), /* PAPR */
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MAKE_64BIT_MASK(0, 8), /* DAMODE */
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MAKE_64BIT_MASK(0, 7), /* PCICMD */
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MAKE_64BIT_MASK(0, 9), /* PCISTS */
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MAKE_64BIT_MASK(0, 32), /* Undefined */
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MAKE_64BIT_MASK(0, 8), /* MLTIM */
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MAKE_64BIT_MASK(0, 30), /* BRDG_FEAT */
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MAKE_64BIT_MASK(0, 24), /* PCIROR */
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MAKE_64BIT_MASK(0, 22), /* PCIWOR */
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MAKE_64BIT_MASK(0, 32), /* Undocumented */
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MAKE_64BIT_MASK(0, 9), /* TLTIM */
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};
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typedef struct DinoState {
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PCIHostState parent_obj;
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/* PCI_CONFIG_ADDR is parent_obj.config_reg, via pci_host_conf_be_ops,
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so that we can map PCI_CONFIG_DATA to pci_host_data_be_ops. */
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uint32_t config_reg_dino; /* keep original copy, including 2 lowest bits */
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uint32_t iar0;
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uint32_t iar1;
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uint32_t imr;
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uint32_t ipr;
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uint32_t icr;
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uint32_t ilr;
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uint32_t io_fbb_en;
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uint32_t io_addr_en;
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uint32_t io_control;
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uint32_t toc_addr;
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uint32_t reg800[DINO800_REGS];
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MemoryRegion this_mem;
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MemoryRegion pci_mem;
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MemoryRegion pci_mem_alias[32];
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AddressSpace bm_as;
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MemoryRegion bm;
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MemoryRegion bm_ram_alias;
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MemoryRegion bm_pci_alias;
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MemoryRegion bm_cpu_alias;
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} DinoState;
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/*
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* Dino can forward memory accesses from the CPU in the range between
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* 0xf0800000 and 0xff000000 to the PCI bus.
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*/
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static void gsc_to_pci_forwarding(DinoState *s)
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{
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uint32_t io_addr_en, tmp;
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int enabled, i;
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tmp = extract32(s->io_control, 7, 2);
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enabled = (tmp == 0x01);
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io_addr_en = s->io_addr_en;
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/* Mask out first (=firmware) and last (=Dino) areas. */
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io_addr_en &= ~(BIT(31) | BIT(0));
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memory_region_transaction_begin();
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for (i = 1; i < 31; i++) {
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MemoryRegion *mem = &s->pci_mem_alias[i];
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if (enabled && (io_addr_en & (1U << i))) {
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if (!memory_region_is_mapped(mem)) {
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uint32_t addr = 0xf0000000 + i * DINO_MEM_CHUNK_SIZE;
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memory_region_add_subregion(get_system_memory(), addr, mem);
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}
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} else if (memory_region_is_mapped(mem)) {
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memory_region_del_subregion(get_system_memory(), mem);
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}
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}
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memory_region_transaction_commit();
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}
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static bool dino_chip_mem_valid(void *opaque, hwaddr addr,
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unsigned size, bool is_write,
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MemTxAttrs attrs)
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{
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bool ret = false;
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switch (addr) {
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case DINO_IAR0:
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case DINO_IAR1:
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case DINO_IRR0:
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case DINO_IRR1:
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case DINO_IMR:
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case DINO_IPR:
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case DINO_ICR:
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case DINO_ILR:
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case DINO_IO_CONTROL:
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case DINO_IO_FBB_EN:
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case DINO_IO_ADDR_EN:
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case DINO_PCI_IO_DATA:
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case DINO_TOC_ADDR:
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case DINO_GMASK ... DINO_PCISTS:
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case DINO_MLTIM ... DINO_PCIWOR:
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case DINO_TLTIM:
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ret = true;
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break;
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case DINO_PCI_IO_DATA + 2:
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ret = (size <= 2);
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break;
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case DINO_PCI_IO_DATA + 1:
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case DINO_PCI_IO_DATA + 3:
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ret = (size == 1);
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}
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trace_dino_chip_mem_valid(addr, ret);
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return ret;
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}
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static MemTxResult dino_chip_read_with_attrs(void *opaque, hwaddr addr,
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uint64_t *data, unsigned size,
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MemTxAttrs attrs)
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{
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DinoState *s = opaque;
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MemTxResult ret = MEMTX_OK;
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AddressSpace *io;
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uint16_t ioaddr;
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uint32_t val;
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switch (addr) {
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case DINO_PCI_IO_DATA ... DINO_PCI_IO_DATA + 3:
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/* Read from PCI IO space. */
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io = &address_space_io;
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ioaddr = s->parent_obj.config_reg + (addr & 3);
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switch (size) {
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case 1:
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val = address_space_ldub(io, ioaddr, attrs, &ret);
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break;
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case 2:
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val = address_space_lduw_be(io, ioaddr, attrs, &ret);
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break;
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case 4:
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val = address_space_ldl_be(io, ioaddr, attrs, &ret);
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break;
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default:
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g_assert_not_reached();
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}
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break;
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case DINO_IO_FBB_EN:
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val = s->io_fbb_en;
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break;
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case DINO_IO_ADDR_EN:
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val = s->io_addr_en;
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break;
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case DINO_IO_CONTROL:
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val = s->io_control;
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break;
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case DINO_IAR0:
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val = s->iar0;
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break;
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case DINO_IAR1:
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val = s->iar1;
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break;
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case DINO_IMR:
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val = s->imr;
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break;
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case DINO_ICR:
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val = s->icr;
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break;
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case DINO_IPR:
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val = s->ipr;
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/* Any read to IPR clears the register. */
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s->ipr = 0;
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break;
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case DINO_ILR:
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val = s->ilr;
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break;
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case DINO_IRR0:
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val = s->ilr & s->imr & ~s->icr;
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break;
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case DINO_IRR1:
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val = s->ilr & s->imr & s->icr;
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break;
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case DINO_TOC_ADDR:
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val = s->toc_addr;
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break;
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case DINO_GMASK ... DINO_TLTIM:
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val = s->reg800[(addr - DINO_GMASK) / 4];
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if (addr == DINO_PAMR) {
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val &= ~0x01; /* LSB is hardwired to 0 */
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}
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if (addr == DINO_MLTIM) {
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val &= ~0x07; /* 3 LSB are hardwired to 0 */
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}
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if (addr == DINO_BRDG_FEAT) {
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val &= ~(0x10710E0ul | 8); /* bits 5-7, 24 & 15 reserved */
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}
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break;
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default:
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/* Controlled by dino_chip_mem_valid above. */
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g_assert_not_reached();
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}
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trace_dino_chip_read(addr, val);
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*data = val;
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return ret;
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}
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static MemTxResult dino_chip_write_with_attrs(void *opaque, hwaddr addr,
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uint64_t val, unsigned size,
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MemTxAttrs attrs)
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{
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DinoState *s = opaque;
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AddressSpace *io;
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MemTxResult ret;
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uint16_t ioaddr;
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int i;
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trace_dino_chip_write(addr, val);
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switch (addr) {
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case DINO_IO_DATA ... DINO_PCI_IO_DATA + 3:
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/* Write into PCI IO space. */
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io = &address_space_io;
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ioaddr = s->parent_obj.config_reg + (addr & 3);
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switch (size) {
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case 1:
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address_space_stb(io, ioaddr, val, attrs, &ret);
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break;
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case 2:
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address_space_stw_be(io, ioaddr, val, attrs, &ret);
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break;
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case 4:
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address_space_stl_be(io, ioaddr, val, attrs, &ret);
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break;
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default:
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g_assert_not_reached();
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}
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return ret;
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case DINO_IO_FBB_EN:
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s->io_fbb_en = val & 0x03;
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break;
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case DINO_IO_ADDR_EN:
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s->io_addr_en = val;
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gsc_to_pci_forwarding(s);
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break;
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case DINO_IO_CONTROL:
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s->io_control = val;
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gsc_to_pci_forwarding(s);
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break;
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case DINO_IAR0:
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s->iar0 = val;
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break;
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case DINO_IAR1:
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s->iar1 = val;
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break;
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case DINO_IMR:
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s->imr = val;
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break;
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case DINO_ICR:
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s->icr = val;
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break;
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case DINO_IPR:
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/* Any write to IPR clears the register. */
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s->ipr = 0;
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break;
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case DINO_TOC_ADDR:
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/* IO_COMMAND of CPU with client_id bits */
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s->toc_addr = 0xFFFA0030 | (val & 0x1e000);
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break;
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case DINO_ILR:
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case DINO_IRR0:
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case DINO_IRR1:
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|
|
/* These registers are read-only. */
|
||
|
|
break;
|
||
|
|
|
||
|
|
case DINO_GMASK ... DINO_TLTIM:
|
||
|
|
i = (addr - DINO_GMASK) / 4;
|
||
|
|
val &= reg800_keep_bits[i];
|
||
|
|
s->reg800[i] = val;
|
||
|
|
break;
|
||
|
|
|
||
|
|
default:
|
||
|
|
/* Controlled by dino_chip_mem_valid above. */
|
||
|
|
g_assert_not_reached();
|
||
|
|
}
|
||
|
|
return MEMTX_OK;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const MemoryRegionOps dino_chip_ops = {
|
||
|
|
.read_with_attrs = dino_chip_read_with_attrs,
|
||
|
|
.write_with_attrs = dino_chip_write_with_attrs,
|
||
|
|
.endianness = DEVICE_BIG_ENDIAN,
|
||
|
|
.valid = {
|
||
|
|
.min_access_size = 1,
|
||
|
|
.max_access_size = 4,
|
||
|
|
.accepts = dino_chip_mem_valid,
|
||
|
|
},
|
||
|
|
.impl = {
|
||
|
|
.min_access_size = 1,
|
||
|
|
.max_access_size = 4,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static const VMStateDescription vmstate_dino = {
|
||
|
|
.name = "Dino",
|
||
|
|
.version_id = 2,
|
||
|
|
.minimum_version_id = 1,
|
||
|
|
.fields = (VMStateField[]) {
|
||
|
|
VMSTATE_UINT32(iar0, DinoState),
|
||
|
|
VMSTATE_UINT32(iar1, DinoState),
|
||
|
|
VMSTATE_UINT32(imr, DinoState),
|
||
|
|
VMSTATE_UINT32(ipr, DinoState),
|
||
|
|
VMSTATE_UINT32(icr, DinoState),
|
||
|
|
VMSTATE_UINT32(ilr, DinoState),
|
||
|
|
VMSTATE_UINT32(io_fbb_en, DinoState),
|
||
|
|
VMSTATE_UINT32(io_addr_en, DinoState),
|
||
|
|
VMSTATE_UINT32(io_control, DinoState),
|
||
|
|
VMSTATE_UINT32(toc_addr, DinoState),
|
||
|
|
VMSTATE_END_OF_LIST()
|
||
|
|
}
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Unlike pci_config_data_le_ops, no check of high bit set in config_reg. */
|
||
|
|
|
||
|
|
static uint64_t dino_config_data_read(void *opaque, hwaddr addr, unsigned len)
|
||
|
|
{
|
||
|
|
PCIHostState *s = opaque;
|
||
|
|
return pci_data_read(s->bus, s->config_reg | (addr & 3), len);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void dino_config_data_write(void *opaque, hwaddr addr,
|
||
|
|
uint64_t val, unsigned len)
|
||
|
|
{
|
||
|
|
PCIHostState *s = opaque;
|
||
|
|
pci_data_write(s->bus, s->config_reg | (addr & 3), val, len);
|
||
|
|
}
|
||
|
|
|
||
|
|
static const MemoryRegionOps dino_config_data_ops = {
|
||
|
|
.read = dino_config_data_read,
|
||
|
|
.write = dino_config_data_write,
|
||
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
||
|
|
};
|
||
|
|
|
||
|
|
static uint64_t dino_config_addr_read(void *opaque, hwaddr addr, unsigned len)
|
||
|
|
{
|
||
|
|
DinoState *s = opaque;
|
||
|
|
return s->config_reg_dino;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void dino_config_addr_write(void *opaque, hwaddr addr,
|
||
|
|
uint64_t val, unsigned len)
|
||
|
|
{
|
||
|
|
PCIHostState *s = opaque;
|
||
|
|
DinoState *ds = opaque;
|
||
|
|
ds->config_reg_dino = val; /* keep a copy of original value */
|
||
|
|
s->config_reg = val & ~3U;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const MemoryRegionOps dino_config_addr_ops = {
|
||
|
|
.read = dino_config_addr_read,
|
||
|
|
.write = dino_config_addr_write,
|
||
|
|
.valid.min_access_size = 4,
|
||
|
|
.valid.max_access_size = 4,
|
||
|
|
.endianness = DEVICE_BIG_ENDIAN,
|
||
|
|
};
|
||
|
|
|
||
|
|
static AddressSpace *dino_pcihost_set_iommu(PCIBus *bus, void *opaque,
|
||
|
|
int devfn)
|
||
|
|
{
|
||
|
|
DinoState *s = opaque;
|
||
|
|
|
||
|
|
return &s->bm_as;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Dino interrupts are connected as shown on Page 78, Table 23
|
||
|
|
* (Little-endian bit numbers)
|
||
|
|
* 0 PCI INTA
|
||
|
|
* 1 PCI INTB
|
||
|
|
* 2 PCI INTC
|
||
|
|
* 3 PCI INTD
|
||
|
|
* 4 PCI INTE
|
||
|
|
* 5 PCI INTF
|
||
|
|
* 6 GSC External Interrupt
|
||
|
|
* 7 Bus Error for "less than fatal" mode
|
||
|
|
* 8 PS2
|
||
|
|
* 9 Unused
|
||
|
|
* 10 RS232
|
||
|
|
*/
|
||
|
|
|
||
|
|
static void dino_set_irq(void *opaque, int irq, int level)
|
||
|
|
{
|
||
|
|
DinoState *s = opaque;
|
||
|
|
uint32_t bit = 1u << irq;
|
||
|
|
uint32_t old_ilr = s->ilr;
|
||
|
|
|
||
|
|
if (level) {
|
||
|
|
uint32_t ena = bit & ~old_ilr;
|
||
|
|
s->ipr |= ena;
|
||
|
|
s->ilr = old_ilr | bit;
|
||
|
|
if (ena & s->imr) {
|
||
|
|
uint32_t iar = (ena & s->icr ? s->iar1 : s->iar0);
|
||
|
|
stl_be_phys(&address_space_memory, iar & -32, iar & 31);
|
||
|
|
}
|
||
|
|
} else {
|
||
|
|
s->ilr = old_ilr & ~bit;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static int dino_pci_map_irq(PCIDevice *d, int irq_num)
|
||
|
|
{
|
||
|
|
int slot = d->devfn >> 3;
|
||
|
|
|
||
|
|
assert(irq_num >= 0 && irq_num <= 3);
|
||
|
|
|
||
|
|
return slot & 0x03;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void dino_set_timer_irq(void *opaque, int irq, int level)
|
||
|
|
{
|
||
|
|
/* ??? Not connected. */
|
||
|
|
}
|
||
|
|
|
||
|
|
static void dino_set_serial_irq(void *opaque, int irq, int level)
|
||
|
|
{
|
||
|
|
dino_set_irq(opaque, 10, level);
|
||
|
|
}
|
||
|
|
|
||
|
|
PCIBus *dino_init(MemoryRegion *addr_space,
|
||
|
|
qemu_irq *p_rtc_irq, qemu_irq *p_ser_irq)
|
||
|
|
{
|
||
|
|
DeviceState *dev;
|
||
|
|
DinoState *s;
|
||
|
|
PCIBus *b;
|
||
|
|
int i;
|
||
|
|
|
||
|
|
dev = qdev_new(TYPE_DINO_PCI_HOST_BRIDGE);
|
||
|
|
s = DINO_PCI_HOST_BRIDGE(dev);
|
||
|
|
s->iar0 = s->iar1 = CPU_HPA + 3;
|
||
|
|
s->toc_addr = 0xFFFA0030; /* IO_COMMAND of CPU */
|
||
|
|
|
||
|
|
/* Dino PCI access from main memory. */
|
||
|
|
memory_region_init_io(&s->this_mem, OBJECT(s), &dino_chip_ops,
|
||
|
|
s, "dino", 4096);
|
||
|
|
memory_region_add_subregion(addr_space, DINO_HPA, &s->this_mem);
|
||
|
|
|
||
|
|
/* Dino PCI config. */
|
||
|
|
memory_region_init_io(&s->parent_obj.conf_mem, OBJECT(&s->parent_obj),
|
||
|
|
&dino_config_addr_ops, dev, "pci-conf-idx", 4);
|
||
|
|
memory_region_init_io(&s->parent_obj.data_mem, OBJECT(&s->parent_obj),
|
||
|
|
&dino_config_data_ops, dev, "pci-conf-data", 4);
|
||
|
|
memory_region_add_subregion(&s->this_mem, DINO_PCI_CONFIG_ADDR,
|
||
|
|
&s->parent_obj.conf_mem);
|
||
|
|
memory_region_add_subregion(&s->this_mem, DINO_CONFIG_DATA,
|
||
|
|
&s->parent_obj.data_mem);
|
||
|
|
|
||
|
|
/* Dino PCI bus memory. */
|
||
|
|
memory_region_init(&s->pci_mem, OBJECT(s), "pci-memory", 4 * GiB);
|
||
|
|
|
||
|
|
b = pci_register_root_bus(dev, "pci", dino_set_irq, dino_pci_map_irq, s,
|
||
|
|
&s->pci_mem, get_system_io(),
|
||
|
|
PCI_DEVFN(0, 0), 32, TYPE_PCI_BUS);
|
||
|
|
s->parent_obj.bus = b;
|
||
|
|
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
|
||
|
|
|
||
|
|
/* Set up windows into PCI bus memory. */
|
||
|
|
for (i = 1; i < 31; i++) {
|
||
|
|
uint32_t addr = 0xf0000000 + i * DINO_MEM_CHUNK_SIZE;
|
||
|
|
char *name = g_strdup_printf("PCI Outbound Window %d", i);
|
||
|
|
memory_region_init_alias(&s->pci_mem_alias[i], OBJECT(s),
|
||
|
|
name, &s->pci_mem, addr,
|
||
|
|
DINO_MEM_CHUNK_SIZE);
|
||
|
|
g_free(name);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Set up PCI view of memory: Bus master address space. */
|
||
|
|
memory_region_init(&s->bm, OBJECT(s), "bm-dino", 4 * GiB);
|
||
|
|
memory_region_init_alias(&s->bm_ram_alias, OBJECT(s),
|
||
|
|
"bm-system", addr_space, 0,
|
||
|
|
0xf0000000 + DINO_MEM_CHUNK_SIZE);
|
||
|
|
memory_region_init_alias(&s->bm_pci_alias, OBJECT(s),
|
||
|
|
"bm-pci", &s->pci_mem,
|
||
|
|
0xf0000000 + DINO_MEM_CHUNK_SIZE,
|
||
|
|
30 * DINO_MEM_CHUNK_SIZE);
|
||
|
|
memory_region_init_alias(&s->bm_cpu_alias, OBJECT(s),
|
||
|
|
"bm-cpu", addr_space, 0xfff00000,
|
||
|
|
0xfffff);
|
||
|
|
memory_region_add_subregion(&s->bm, 0,
|
||
|
|
&s->bm_ram_alias);
|
||
|
|
memory_region_add_subregion(&s->bm,
|
||
|
|
0xf0000000 + DINO_MEM_CHUNK_SIZE,
|
||
|
|
&s->bm_pci_alias);
|
||
|
|
memory_region_add_subregion(&s->bm, 0xfff00000,
|
||
|
|
&s->bm_cpu_alias);
|
||
|
|
address_space_init(&s->bm_as, &s->bm, "pci-bm");
|
||
|
|
pci_setup_iommu(b, dino_pcihost_set_iommu, s);
|
||
|
|
|
||
|
|
*p_rtc_irq = qemu_allocate_irq(dino_set_timer_irq, s, 0);
|
||
|
|
*p_ser_irq = qemu_allocate_irq(dino_set_serial_irq, s, 0);
|
||
|
|
|
||
|
|
return b;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void dino_pcihost_class_init(ObjectClass *klass, void *data)
|
||
|
|
{
|
||
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
||
|
|
|
||
|
|
dc->vmsd = &vmstate_dino;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const TypeInfo dino_pcihost_info = {
|
||
|
|
.name = TYPE_DINO_PCI_HOST_BRIDGE,
|
||
|
|
.parent = TYPE_PCI_HOST_BRIDGE,
|
||
|
|
.instance_size = sizeof(DinoState),
|
||
|
|
.class_init = dino_pcihost_class_init,
|
||
|
|
};
|
||
|
|
|
||
|
|
static void dino_register_types(void)
|
||
|
|
{
|
||
|
|
type_register_static(&dino_pcihost_info);
|
||
|
|
}
|
||
|
|
|
||
|
|
type_init(dino_register_types)
|