367 lines
11 KiB
C
367 lines
11 KiB
C
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/*
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* i.MX31 Vectored Interrupt Controller
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*
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* Note this is NOT the PL192 provided by ARM, but
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* a custom implementation by Freescale.
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*
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* Copyright (c) 2008 OKL
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* Copyright (c) 2011 NICTA Pty Ltd
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* Originally written by Hans Jiang
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* Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*
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* TODO: implement vectors.
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*/
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#include "qemu/osdep.h"
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#include "hw/intc/imx_avic.h"
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#include "hw/irq.h"
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#include "migration/vmstate.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#ifndef DEBUG_IMX_AVIC
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#define DEBUG_IMX_AVIC 0
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#endif
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#define DPRINTF(fmt, args...) \
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do { \
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if (DEBUG_IMX_AVIC) { \
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fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_AVIC, \
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__func__, ##args); \
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} \
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} while (0)
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static const VMStateDescription vmstate_imx_avic = {
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.name = TYPE_IMX_AVIC,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(pending, IMXAVICState),
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VMSTATE_UINT64(enabled, IMXAVICState),
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VMSTATE_UINT64(is_fiq, IMXAVICState),
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VMSTATE_UINT32(intcntl, IMXAVICState),
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VMSTATE_UINT32(intmask, IMXAVICState),
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VMSTATE_UINT32_ARRAY(prio, IMXAVICState, PRIO_WORDS),
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VMSTATE_END_OF_LIST()
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},
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};
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static inline int imx_avic_prio(IMXAVICState *s, int irq)
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{
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uint32_t word = irq / PRIO_PER_WORD;
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uint32_t part = 4 * (irq % PRIO_PER_WORD);
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return 0xf & (s->prio[word] >> part);
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}
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/* Update interrupts. */
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static void imx_avic_update(IMXAVICState *s)
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{
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int i;
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uint64_t new = s->pending & s->enabled;
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uint64_t flags;
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flags = new & s->is_fiq;
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qemu_set_irq(s->fiq, !!flags);
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flags = new & ~s->is_fiq;
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if (!flags || (s->intmask == 0x1f)) {
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qemu_set_irq(s->irq, !!flags);
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return;
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}
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/*
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* Take interrupt if there's a pending interrupt with
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* priority higher than the value of intmask
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*/
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for (i = 0; i < IMX_AVIC_NUM_IRQS; i++) {
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if (flags & (1UL << i)) {
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if (imx_avic_prio(s, i) > s->intmask) {
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qemu_set_irq(s->irq, 1);
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return;
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}
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}
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}
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qemu_set_irq(s->irq, 0);
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}
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static void imx_avic_set_irq(void *opaque, int irq, int level)
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{
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IMXAVICState *s = (IMXAVICState *)opaque;
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if (level) {
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DPRINTF("Raising IRQ %d, prio %d\n",
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irq, imx_avic_prio(s, irq));
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s->pending |= (1ULL << irq);
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} else {
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DPRINTF("Clearing IRQ %d, prio %d\n",
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irq, imx_avic_prio(s, irq));
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s->pending &= ~(1ULL << irq);
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}
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imx_avic_update(s);
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}
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static uint64_t imx_avic_read(void *opaque,
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hwaddr offset, unsigned size)
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{
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IMXAVICState *s = (IMXAVICState *)opaque;
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DPRINTF("read(offset = 0x%" HWADDR_PRIx ")\n", offset);
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switch (offset >> 2) {
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case 0: /* INTCNTL */
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return s->intcntl;
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case 1: /* Normal Interrupt Mask Register, NIMASK */
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return s->intmask;
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case 2: /* Interrupt Enable Number Register, INTENNUM */
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case 3: /* Interrupt Disable Number Register, INTDISNUM */
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return 0;
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case 4: /* Interrupt Enabled Number Register High */
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return s->enabled >> 32;
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case 5: /* Interrupt Enabled Number Register Low */
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return s->enabled & 0xffffffffULL;
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case 6: /* Interrupt Type Register High */
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return s->is_fiq >> 32;
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case 7: /* Interrupt Type Register Low */
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return s->is_fiq & 0xffffffffULL;
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case 8: /* Normal Interrupt Priority Register 7 */
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case 9: /* Normal Interrupt Priority Register 6 */
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case 10:/* Normal Interrupt Priority Register 5 */
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case 11:/* Normal Interrupt Priority Register 4 */
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case 12:/* Normal Interrupt Priority Register 3 */
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case 13:/* Normal Interrupt Priority Register 2 */
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case 14:/* Normal Interrupt Priority Register 1 */
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case 15:/* Normal Interrupt Priority Register 0 */
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return s->prio[15-(offset>>2)];
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case 16: /* Normal interrupt vector and status register */
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{
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/*
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* This returns the highest priority
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* outstanding interrupt. Where there is more than
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* one pending IRQ with the same priority,
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* take the highest numbered one.
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*/
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uint64_t flags = s->pending & s->enabled & ~s->is_fiq;
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int i;
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int prio = -1;
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int irq = -1;
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for (i = 63; i >= 0; --i) {
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if (flags & (1ULL<<i)) {
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int irq_prio = imx_avic_prio(s, i);
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if (irq_prio > prio) {
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irq = i;
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prio = irq_prio;
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}
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}
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}
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if (irq >= 0) {
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imx_avic_set_irq(s, irq, 0);
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return irq << 16 | prio;
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}
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return 0xffffffffULL;
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}
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case 17:/* Fast Interrupt vector and status register */
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{
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uint64_t flags = s->pending & s->enabled & s->is_fiq;
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int i = ctz64(flags);
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if (i < 64) {
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imx_avic_set_irq(opaque, i, 0);
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return i;
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}
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return 0xffffffffULL;
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}
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case 18:/* Interrupt source register high */
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return s->pending >> 32;
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case 19:/* Interrupt source register low */
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return s->pending & 0xffffffffULL;
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case 20:/* Interrupt Force Register high */
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case 21:/* Interrupt Force Register low */
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return 0;
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case 22:/* Normal Interrupt Pending Register High */
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return (s->pending & s->enabled & ~s->is_fiq) >> 32;
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case 23:/* Normal Interrupt Pending Register Low */
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return (s->pending & s->enabled & ~s->is_fiq) & 0xffffffffULL;
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case 24: /* Fast Interrupt Pending Register High */
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return (s->pending & s->enabled & s->is_fiq) >> 32;
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case 25: /* Fast Interrupt Pending Register Low */
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return (s->pending & s->enabled & s->is_fiq) & 0xffffffffULL;
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case 0x40: /* AVIC vector 0, use for WFI WAR */
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return 0x4;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
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HWADDR_PRIx "\n", TYPE_IMX_AVIC, __func__, offset);
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return 0;
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}
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}
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static void imx_avic_write(void *opaque, hwaddr offset,
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uint64_t val, unsigned size)
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{
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IMXAVICState *s = (IMXAVICState *)opaque;
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/* Vector Registers not yet supported */
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if (offset >= 0x100 && offset <= 0x2fc) {
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qemu_log_mask(LOG_UNIMP, "[%s]%s: vector %d ignored\n",
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TYPE_IMX_AVIC, __func__, (int)((offset - 0x100) >> 2));
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return;
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}
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DPRINTF("(0x%" HWADDR_PRIx ") = 0x%x\n", offset, (unsigned int)val);
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switch (offset >> 2) {
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case 0: /* Interrupt Control Register, INTCNTL */
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s->intcntl = val & (ABFEN | NIDIS | FIDIS | NIAD | FIAD | NM);
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if (s->intcntl & ABFEN) {
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s->intcntl &= ~(val & ABFLAG);
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}
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break;
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case 1: /* Normal Interrupt Mask Register, NIMASK */
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s->intmask = val & 0x1f;
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break;
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case 2: /* Interrupt Enable Number Register, INTENNUM */
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DPRINTF("enable(%d)\n", (int)val);
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val &= 0x3f;
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s->enabled |= (1ULL << val);
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break;
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case 3: /* Interrupt Disable Number Register, INTDISNUM */
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DPRINTF("disable(%d)\n", (int)val);
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val &= 0x3f;
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s->enabled &= ~(1ULL << val);
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break;
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case 4: /* Interrupt Enable Number Register High */
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s->enabled = (s->enabled & 0xffffffffULL) | (val << 32);
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break;
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case 5: /* Interrupt Enable Number Register Low */
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s->enabled = (s->enabled & 0xffffffff00000000ULL) | val;
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break;
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case 6: /* Interrupt Type Register High */
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s->is_fiq = (s->is_fiq & 0xffffffffULL) | (val << 32);
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break;
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case 7: /* Interrupt Type Register Low */
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s->is_fiq = (s->is_fiq & 0xffffffff00000000ULL) | val;
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break;
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case 8: /* Normal Interrupt Priority Register 7 */
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case 9: /* Normal Interrupt Priority Register 6 */
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case 10:/* Normal Interrupt Priority Register 5 */
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case 11:/* Normal Interrupt Priority Register 4 */
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case 12:/* Normal Interrupt Priority Register 3 */
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case 13:/* Normal Interrupt Priority Register 2 */
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case 14:/* Normal Interrupt Priority Register 1 */
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case 15:/* Normal Interrupt Priority Register 0 */
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s->prio[15-(offset>>2)] = val;
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break;
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/* Read-only registers, writes ignored */
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case 16:/* Normal Interrupt Vector and Status register */
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case 17:/* Fast Interrupt vector and status register */
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case 18:/* Interrupt source register high */
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case 19:/* Interrupt source register low */
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return;
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case 20:/* Interrupt Force Register high */
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s->pending = (s->pending & 0xffffffffULL) | (val << 32);
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break;
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case 21:/* Interrupt Force Register low */
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s->pending = (s->pending & 0xffffffff00000000ULL) | val;
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break;
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case 22:/* Normal Interrupt Pending Register High */
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case 23:/* Normal Interrupt Pending Register Low */
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case 24: /* Fast Interrupt Pending Register High */
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case 25: /* Fast Interrupt Pending Register Low */
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return;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
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HWADDR_PRIx "\n", TYPE_IMX_AVIC, __func__, offset);
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}
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imx_avic_update(s);
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}
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static const MemoryRegionOps imx_avic_ops = {
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.read = imx_avic_read,
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.write = imx_avic_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void imx_avic_reset(DeviceState *dev)
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{
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IMXAVICState *s = IMX_AVIC(dev);
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s->pending = 0;
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s->enabled = 0;
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s->is_fiq = 0;
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s->intmask = 0x1f;
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s->intcntl = 0;
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memset(s->prio, 0, sizeof s->prio);
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}
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static void imx_avic_init(Object *obj)
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{
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DeviceState *dev = DEVICE(obj);
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IMXAVICState *s = IMX_AVIC(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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memory_region_init_io(&s->iomem, obj, &imx_avic_ops, s,
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TYPE_IMX_AVIC, 0x1000);
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sysbus_init_mmio(sbd, &s->iomem);
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qdev_init_gpio_in(dev, imx_avic_set_irq, IMX_AVIC_NUM_IRQS);
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sysbus_init_irq(sbd, &s->irq);
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sysbus_init_irq(sbd, &s->fiq);
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}
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static void imx_avic_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->vmsd = &vmstate_imx_avic;
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dc->reset = imx_avic_reset;
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dc->desc = "i.MX Advanced Vector Interrupt Controller";
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}
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static const TypeInfo imx_avic_info = {
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.name = TYPE_IMX_AVIC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(IMXAVICState),
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.instance_init = imx_avic_init,
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.class_init = imx_avic_class_init,
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};
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static void imx_avic_register_types(void)
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{
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type_register_static(&imx_avic_info);
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}
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type_init(imx_avic_register_types)
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