469 lines
16 KiB
C
469 lines
16 KiB
C
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
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* Authors: Sanjay Lal <sanjayl@kymasys.com>
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*
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* Copyright (C) 2016 Imagination Technologies
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "qapi/error.h"
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#include "hw/sysbus.h"
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#include "exec/memory.h"
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#include "sysemu/kvm.h"
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#include "sysemu/reset.h"
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#include "kvm_mips.h"
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#include "hw/intc/mips_gic.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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static void mips_gic_set_vp_irq(MIPSGICState *gic, int vp, int pin)
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{
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int ored_level = 0;
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int i;
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/* ORing pending registers sharing same pin */
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for (i = 0; i < gic->num_irq; i++) {
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if ((gic->irq_state[i].map_pin & GIC_MAP_MSK) == pin &&
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gic->irq_state[i].map_vp == vp &&
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gic->irq_state[i].enabled) {
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ored_level |= gic->irq_state[i].pending;
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}
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if (ored_level) {
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/* no need to iterate all interrupts */
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break;
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}
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}
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if (((gic->vps[vp].compare_map & GIC_MAP_MSK) == pin) &&
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(gic->vps[vp].mask & GIC_VP_MASK_CMP_MSK)) {
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/* ORing with local pending register (count/compare) */
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ored_level |= (gic->vps[vp].pend & GIC_VP_MASK_CMP_MSK) >>
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GIC_VP_MASK_CMP_SHF;
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}
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if (kvm_enabled()) {
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kvm_mips_set_ipi_interrupt(env_archcpu(gic->vps[vp].env),
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pin + GIC_CPU_PIN_OFFSET,
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ored_level);
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} else {
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qemu_set_irq(gic->vps[vp].env->irq[pin + GIC_CPU_PIN_OFFSET],
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ored_level);
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}
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}
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static void gic_update_pin_for_irq(MIPSGICState *gic, int n_IRQ)
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{
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int vp = gic->irq_state[n_IRQ].map_vp;
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int pin = gic->irq_state[n_IRQ].map_pin & GIC_MAP_MSK;
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if (vp < 0 || vp >= gic->num_vps) {
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return;
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}
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mips_gic_set_vp_irq(gic, vp, pin);
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}
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static void gic_set_irq(void *opaque, int n_IRQ, int level)
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{
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MIPSGICState *gic = (MIPSGICState *) opaque;
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gic->irq_state[n_IRQ].pending = (uint8_t) level;
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if (!gic->irq_state[n_IRQ].enabled) {
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/* GIC interrupt source disabled */
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return;
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}
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gic_update_pin_for_irq(gic, n_IRQ);
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}
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#define OFFSET_CHECK(c) \
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do { \
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if (!(c)) { \
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goto bad_offset; \
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} \
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} while (0)
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/* GIC Read VP Local/Other Registers */
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static uint64_t gic_read_vp(MIPSGICState *gic, uint32_t vp_index, hwaddr addr,
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unsigned size)
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{
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switch (addr) {
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case GIC_VP_CTL_OFS:
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return gic->vps[vp_index].ctl;
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case GIC_VP_PEND_OFS:
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mips_gictimer_get_sh_count(gic->gic_timer);
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return gic->vps[vp_index].pend;
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case GIC_VP_MASK_OFS:
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return gic->vps[vp_index].mask;
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case GIC_VP_COMPARE_MAP_OFS:
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return gic->vps[vp_index].compare_map;
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case GIC_VP_OTHER_ADDR_OFS:
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return gic->vps[vp_index].other_addr;
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case GIC_VP_IDENT_OFS:
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return vp_index;
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case GIC_VP_COMPARE_LO_OFS:
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return mips_gictimer_get_vp_compare(gic->gic_timer, vp_index);
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case GIC_VP_COMPARE_HI_OFS:
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return 0;
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default:
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qemu_log_mask(LOG_UNIMP, "Read %d bytes at GIC offset LOCAL/OTHER 0x%"
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PRIx64 "\n", size, addr);
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break;
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}
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return 0;
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}
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static uint64_t gic_read(void *opaque, hwaddr addr, unsigned size)
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{
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MIPSGICState *gic = (MIPSGICState *) opaque;
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uint32_t vp_index = current_cpu->cpu_index;
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uint64_t ret = 0;
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int i, base, irq_src;
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uint32_t other_index;
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switch (addr) {
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case GIC_SH_CONFIG_OFS:
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ret = gic->sh_config | (mips_gictimer_get_countstop(gic->gic_timer) <<
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GIC_SH_CONFIG_COUNTSTOP_SHF);
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break;
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case GIC_SH_COUNTERLO_OFS:
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ret = mips_gictimer_get_sh_count(gic->gic_timer);
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break;
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case GIC_SH_COUNTERHI_OFS:
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ret = 0;
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break;
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case GIC_SH_PEND_OFS ... GIC_SH_PEND_LAST_OFS:
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/* each bit represents pending status for an interrupt pin */
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base = (addr - GIC_SH_PEND_OFS) * 8;
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OFFSET_CHECK((base + size * 8) <= gic->num_irq);
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for (i = 0; i < size * 8; i++) {
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ret |= (uint64_t) (gic->irq_state[base + i].pending) << i;
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}
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break;
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case GIC_SH_MASK_OFS ... GIC_SH_MASK_LAST_OFS:
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/* each bit represents status for an interrupt pin */
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base = (addr - GIC_SH_MASK_OFS) * 8;
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OFFSET_CHECK((base + size * 8) <= gic->num_irq);
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for (i = 0; i < size * 8; i++) {
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ret |= (uint64_t) (gic->irq_state[base + i].enabled) << i;
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}
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break;
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case GIC_SH_MAP0_PIN_OFS ... GIC_SH_MAP255_PIN_OFS:
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/* 32 bits per a pin */
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irq_src = (addr - GIC_SH_MAP0_PIN_OFS) / 4;
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OFFSET_CHECK(irq_src < gic->num_irq);
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ret = gic->irq_state[irq_src].map_pin;
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break;
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case GIC_SH_MAP0_VP_OFS ... GIC_SH_MAP255_VP_LAST_OFS:
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/* up to 32 bytes per a pin */
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irq_src = (addr - GIC_SH_MAP0_VP_OFS) / 32;
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OFFSET_CHECK(irq_src < gic->num_irq);
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if ((gic->irq_state[irq_src].map_vp) >= 0) {
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ret = (uint64_t) 1 << (gic->irq_state[irq_src].map_vp);
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} else {
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ret = 0;
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}
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break;
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/* VP-Local Register */
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case VP_LOCAL_SECTION_OFS ... (VP_LOCAL_SECTION_OFS + GIC_VL_BRK_GROUP):
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ret = gic_read_vp(gic, vp_index, addr - VP_LOCAL_SECTION_OFS, size);
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break;
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/* VP-Other Register */
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case VP_OTHER_SECTION_OFS ... (VP_OTHER_SECTION_OFS + GIC_VL_BRK_GROUP):
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other_index = gic->vps[vp_index].other_addr;
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ret = gic_read_vp(gic, other_index, addr - VP_OTHER_SECTION_OFS, size);
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break;
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/* User-Mode Visible section */
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case USM_VISIBLE_SECTION_OFS + GIC_USER_MODE_COUNTERLO:
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ret = mips_gictimer_get_sh_count(gic->gic_timer);
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break;
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case USM_VISIBLE_SECTION_OFS + GIC_USER_MODE_COUNTERHI:
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ret = 0;
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "Read %d bytes at GIC offset 0x%" PRIx64 "\n",
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size, addr);
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break;
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}
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return ret;
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bad_offset:
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qemu_log_mask(LOG_GUEST_ERROR, "Wrong GIC offset at 0x%" PRIx64 "\n", addr);
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return 0;
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}
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static void gic_timer_expire_cb(void *opaque, uint32_t vp_index)
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{
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MIPSGICState *gic = opaque;
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gic->vps[vp_index].pend |= (1 << GIC_LOCAL_INT_COMPARE);
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if (gic->vps[vp_index].pend &
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(gic->vps[vp_index].mask & GIC_VP_MASK_CMP_MSK)) {
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if (gic->vps[vp_index].compare_map & GIC_MAP_TO_PIN_MSK) {
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/* it is safe to set the irq high regardless of other GIC IRQs */
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uint32_t pin = (gic->vps[vp_index].compare_map & GIC_MAP_MSK);
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qemu_irq_raise(gic->vps[vp_index].env->irq
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[pin + GIC_CPU_PIN_OFFSET]);
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}
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}
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}
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static void gic_timer_store_vp_compare(MIPSGICState *gic, uint32_t vp_index,
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uint64_t compare)
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{
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gic->vps[vp_index].pend &= ~(1 << GIC_LOCAL_INT_COMPARE);
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if (gic->vps[vp_index].compare_map & GIC_MAP_TO_PIN_MSK) {
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uint32_t pin = (gic->vps[vp_index].compare_map & GIC_MAP_MSK);
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mips_gic_set_vp_irq(gic, vp_index, pin);
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}
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mips_gictimer_store_vp_compare(gic->gic_timer, vp_index, compare);
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}
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/* GIC Write VP Local/Other Registers */
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static void gic_write_vp(MIPSGICState *gic, uint32_t vp_index, hwaddr addr,
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uint64_t data, unsigned size)
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{
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switch (addr) {
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case GIC_VP_CTL_OFS:
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/* EIC isn't supported */
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break;
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case GIC_VP_RMASK_OFS:
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gic->vps[vp_index].mask &= ~(data & GIC_VP_SET_RESET_MSK) &
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GIC_VP_SET_RESET_MSK;
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break;
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case GIC_VP_SMASK_OFS:
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gic->vps[vp_index].mask |= data & GIC_VP_SET_RESET_MSK;
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break;
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case GIC_VP_COMPARE_MAP_OFS:
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/* EIC isn't supported */
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OFFSET_CHECK((data & GIC_MAP_MSK) <= GIC_CPU_INT_MAX);
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gic->vps[vp_index].compare_map = data & GIC_MAP_TO_PIN_REG_MSK;
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break;
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case GIC_VP_OTHER_ADDR_OFS:
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OFFSET_CHECK(data < gic->num_vps);
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gic->vps[vp_index].other_addr = data;
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break;
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case GIC_VP_COMPARE_LO_OFS:
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gic_timer_store_vp_compare(gic, vp_index, data);
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "Write %d bytes at GIC offset LOCAL/OTHER "
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"0x%" PRIx64" 0x%08" PRIx64 "\n", size, addr, data);
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break;
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}
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return;
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bad_offset:
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qemu_log_mask(LOG_GUEST_ERROR, "Wrong GIC offset at 0x%" PRIx64 "\n", addr);
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return;
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}
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static void gic_write(void *opaque, hwaddr addr, uint64_t data, unsigned size)
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{
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int intr;
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MIPSGICState *gic = (MIPSGICState *) opaque;
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uint32_t vp_index = current_cpu->cpu_index;
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int i, base, irq_src;
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uint32_t other_index;
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switch (addr) {
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case GIC_SH_CONFIG_OFS:
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{
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uint32_t pre_cntstop = mips_gictimer_get_countstop(gic->gic_timer);
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uint32_t new_cntstop = (data & GIC_SH_CONFIG_COUNTSTOP_MSK) >>
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GIC_SH_CONFIG_COUNTSTOP_SHF;
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if (pre_cntstop != new_cntstop) {
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if (new_cntstop == 1) {
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mips_gictimer_stop_count(gic->gic_timer);
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} else {
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mips_gictimer_start_count(gic->gic_timer);
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}
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}
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}
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break;
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case GIC_SH_COUNTERLO_OFS:
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if (mips_gictimer_get_countstop(gic->gic_timer)) {
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mips_gictimer_store_sh_count(gic->gic_timer, data);
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}
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break;
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case GIC_SH_RMASK_OFS ... GIC_SH_RMASK_LAST_OFS:
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/* up to 64 bits per a pin */
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base = (addr - GIC_SH_RMASK_OFS) * 8;
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OFFSET_CHECK((base + size * 8) <= gic->num_irq);
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for (i = 0; i < size * 8; i++) {
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gic->irq_state[base + i].enabled &= !((data >> i) & 1);
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gic_update_pin_for_irq(gic, base + i);
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}
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break;
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case GIC_SH_WEDGE_OFS:
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/* Figure out which VP/HW Interrupt this maps to */
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intr = data & ~GIC_SH_WEDGE_RW_MSK;
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/* Mask/Enabled Checks */
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OFFSET_CHECK(intr < gic->num_irq);
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if (data & GIC_SH_WEDGE_RW_MSK) {
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gic_set_irq(gic, intr, 1);
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} else {
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gic_set_irq(gic, intr, 0);
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}
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break;
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case GIC_SH_SMASK_OFS ... GIC_SH_SMASK_LAST_OFS:
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/* up to 64 bits per a pin */
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base = (addr - GIC_SH_SMASK_OFS) * 8;
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OFFSET_CHECK((base + size * 8) <= gic->num_irq);
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for (i = 0; i < size * 8; i++) {
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gic->irq_state[base + i].enabled |= (data >> i) & 1;
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gic_update_pin_for_irq(gic, base + i);
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}
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break;
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case GIC_SH_MAP0_PIN_OFS ... GIC_SH_MAP255_PIN_OFS:
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/* 32 bits per a pin */
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irq_src = (addr - GIC_SH_MAP0_PIN_OFS) / 4;
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OFFSET_CHECK(irq_src < gic->num_irq);
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||
|
|
/* EIC isn't supported */
|
||
|
|
OFFSET_CHECK((data & GIC_MAP_MSK) <= GIC_CPU_INT_MAX);
|
||
|
|
gic->irq_state[irq_src].map_pin = data & GIC_MAP_TO_PIN_REG_MSK;
|
||
|
|
break;
|
||
|
|
case GIC_SH_MAP0_VP_OFS ... GIC_SH_MAP255_VP_LAST_OFS:
|
||
|
|
/* up to 32 bytes per a pin */
|
||
|
|
irq_src = (addr - GIC_SH_MAP0_VP_OFS) / 32;
|
||
|
|
OFFSET_CHECK(irq_src < gic->num_irq);
|
||
|
|
data = data ? ctz64(data) : -1;
|
||
|
|
OFFSET_CHECK(data < gic->num_vps);
|
||
|
|
gic->irq_state[irq_src].map_vp = data;
|
||
|
|
break;
|
||
|
|
case VP_LOCAL_SECTION_OFS ... (VP_LOCAL_SECTION_OFS + GIC_VL_BRK_GROUP):
|
||
|
|
gic_write_vp(gic, vp_index, addr - VP_LOCAL_SECTION_OFS, data, size);
|
||
|
|
break;
|
||
|
|
case VP_OTHER_SECTION_OFS ... (VP_OTHER_SECTION_OFS + GIC_VL_BRK_GROUP):
|
||
|
|
other_index = gic->vps[vp_index].other_addr;
|
||
|
|
gic_write_vp(gic, other_index, addr - VP_OTHER_SECTION_OFS, data, size);
|
||
|
|
break;
|
||
|
|
case USM_VISIBLE_SECTION_OFS + GIC_USER_MODE_COUNTERLO:
|
||
|
|
case USM_VISIBLE_SECTION_OFS + GIC_USER_MODE_COUNTERHI:
|
||
|
|
/* do nothing. Read-only section */
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
qemu_log_mask(LOG_UNIMP, "Write %d bytes at GIC offset 0x%" PRIx64
|
||
|
|
" 0x%08" PRIx64 "\n", size, addr, data);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
return;
|
||
|
|
bad_offset:
|
||
|
|
qemu_log_mask(LOG_GUEST_ERROR, "Wrong GIC offset at 0x%" PRIx64 "\n", addr);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void gic_reset(void *opaque)
|
||
|
|
{
|
||
|
|
int i;
|
||
|
|
MIPSGICState *gic = (MIPSGICState *) opaque;
|
||
|
|
int numintrs = (gic->num_irq / 8) - 1;
|
||
|
|
|
||
|
|
gic->sh_config = /* COUNTSTOP = 0 it is accessible via MIPSGICTimer*/
|
||
|
|
/* CounterHi not implemented */
|
||
|
|
(0 << GIC_SH_CONFIG_COUNTBITS_SHF) |
|
||
|
|
(numintrs << GIC_SH_CONFIG_NUMINTRS_SHF) |
|
||
|
|
(gic->num_vps << GIC_SH_CONFIG_PVPS_SHF);
|
||
|
|
for (i = 0; i < gic->num_vps; i++) {
|
||
|
|
gic->vps[i].ctl = 0x0;
|
||
|
|
gic->vps[i].pend = 0x0;
|
||
|
|
/* PERFCNT, TIMER and WD not implemented */
|
||
|
|
gic->vps[i].mask = 0x32;
|
||
|
|
gic->vps[i].compare_map = GIC_MAP_TO_PIN_MSK;
|
||
|
|
mips_gictimer_store_vp_compare(gic->gic_timer, i, 0xffffffff);
|
||
|
|
gic->vps[i].other_addr = 0x0;
|
||
|
|
}
|
||
|
|
for (i = 0; i < gic->num_irq; i++) {
|
||
|
|
gic->irq_state[i].enabled = 0;
|
||
|
|
gic->irq_state[i].pending = 0;
|
||
|
|
gic->irq_state[i].map_pin = GIC_MAP_TO_PIN_MSK;
|
||
|
|
gic->irq_state[i].map_vp = -1;
|
||
|
|
}
|
||
|
|
mips_gictimer_store_sh_count(gic->gic_timer, 0);
|
||
|
|
/* COUNTSTOP = 0 */
|
||
|
|
mips_gictimer_start_count(gic->gic_timer);
|
||
|
|
}
|
||
|
|
|
||
|
|
static const MemoryRegionOps gic_ops = {
|
||
|
|
.read = gic_read,
|
||
|
|
.write = gic_write,
|
||
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
||
|
|
.impl = {
|
||
|
|
.max_access_size = 8,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static void mips_gic_init(Object *obj)
|
||
|
|
{
|
||
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
|
||
|
|
MIPSGICState *s = MIPS_GIC(obj);
|
||
|
|
|
||
|
|
memory_region_init_io(&s->mr, OBJECT(s), &gic_ops, s,
|
||
|
|
"mips-gic", GIC_ADDRSPACE_SZ);
|
||
|
|
sysbus_init_mmio(sbd, &s->mr);
|
||
|
|
qemu_register_reset(gic_reset, s);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void mips_gic_realize(DeviceState *dev, Error **errp)
|
||
|
|
{
|
||
|
|
MIPSGICState *s = MIPS_GIC(dev);
|
||
|
|
CPUState *cs = first_cpu;
|
||
|
|
int i;
|
||
|
|
|
||
|
|
if (s->num_vps > GIC_MAX_VPS) {
|
||
|
|
error_setg(errp, "Exceeded maximum CPUs %d", s->num_vps);
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
if ((s->num_irq > GIC_MAX_INTRS) || (s->num_irq % 8) || (s->num_irq <= 0)) {
|
||
|
|
error_setg(errp, "GIC supports up to %d external interrupts in "
|
||
|
|
"multiples of 8 : %d", GIC_MAX_INTRS, s->num_irq);
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
s->vps = g_new(MIPSGICVPState, s->num_vps);
|
||
|
|
s->irq_state = g_new(MIPSGICIRQState, s->num_irq);
|
||
|
|
/* Register the env for all VPs with the GIC */
|
||
|
|
for (i = 0; i < s->num_vps; i++) {
|
||
|
|
if (cs != NULL) {
|
||
|
|
s->vps[i].env = cs->env_ptr;
|
||
|
|
cs = CPU_NEXT(cs);
|
||
|
|
} else {
|
||
|
|
error_setg(errp,
|
||
|
|
"Unable to initialize GIC, CPUState for CPU#%d not valid.", i);
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
s->gic_timer = mips_gictimer_init(s, s->num_vps, gic_timer_expire_cb);
|
||
|
|
qdev_init_gpio_in(dev, gic_set_irq, s->num_irq);
|
||
|
|
for (i = 0; i < s->num_irq; i++) {
|
||
|
|
s->irq_state[i].irq = qdev_get_gpio_in(dev, i);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static Property mips_gic_properties[] = {
|
||
|
|
DEFINE_PROP_INT32("num-vp", MIPSGICState, num_vps, 1),
|
||
|
|
DEFINE_PROP_INT32("num-irq", MIPSGICState, num_irq, 256),
|
||
|
|
DEFINE_PROP_END_OF_LIST(),
|
||
|
|
};
|
||
|
|
|
||
|
|
static void mips_gic_class_init(ObjectClass *klass, void *data)
|
||
|
|
{
|
||
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
||
|
|
|
||
|
|
device_class_set_props(dc, mips_gic_properties);
|
||
|
|
dc->realize = mips_gic_realize;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const TypeInfo mips_gic_info = {
|
||
|
|
.name = TYPE_MIPS_GIC,
|
||
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
||
|
|
.instance_size = sizeof(MIPSGICState),
|
||
|
|
.instance_init = mips_gic_init,
|
||
|
|
.class_init = mips_gic_class_init,
|
||
|
|
};
|
||
|
|
|
||
|
|
static void mips_gic_register_types(void)
|
||
|
|
{
|
||
|
|
type_register_static(&mips_gic_info);
|
||
|
|
}
|
||
|
|
|
||
|
|
type_init(mips_gic_register_types)
|