554 lines
18 KiB
C
554 lines
18 KiB
C
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/*
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* MIPS Boston development board emulation.
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*
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* Copyright (c) 2016 Imagination Technologies
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "exec/address-spaces.h"
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#include "hw/boards.h"
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#include "hw/char/serial.h"
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#include "hw/ide/pci.h"
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#include "hw/ide/ahci.h"
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#include "hw/loader.h"
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#include "hw/loader-fit.h"
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#include "hw/mips/cps.h"
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#include "hw/mips/cpudevs.h"
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#include "hw/pci-host/xilinx-pcie.h"
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#include "hw/qdev-properties.h"
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#include "qapi/error.h"
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#include "qemu/error-report.h"
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#include "qemu/log.h"
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#include "chardev/char.h"
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#include "sysemu/device_tree.h"
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#include "sysemu/sysemu.h"
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#include "sysemu/qtest.h"
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#include "sysemu/runstate.h"
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#include <libfdt.h>
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#define TYPE_MIPS_BOSTON "mips-boston"
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#define BOSTON(obj) OBJECT_CHECK(BostonState, (obj), TYPE_MIPS_BOSTON)
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typedef struct {
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SysBusDevice parent_obj;
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MachineState *mach;
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MIPSCPSState cps;
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SerialMM *uart;
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CharBackend lcd_display;
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char lcd_content[8];
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bool lcd_inited;
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hwaddr kernel_entry;
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hwaddr fdt_base;
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} BostonState;
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enum boston_plat_reg {
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PLAT_FPGA_BUILD = 0x00,
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PLAT_CORE_CL = 0x04,
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PLAT_WRAPPER_CL = 0x08,
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PLAT_SYSCLK_STATUS = 0x0c,
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PLAT_SOFTRST_CTL = 0x10,
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#define PLAT_SOFTRST_CTL_SYSRESET (1 << 4)
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PLAT_DDR3_STATUS = 0x14,
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#define PLAT_DDR3_STATUS_LOCKED (1 << 0)
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#define PLAT_DDR3_STATUS_CALIBRATED (1 << 2)
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PLAT_PCIE_STATUS = 0x18,
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#define PLAT_PCIE_STATUS_PCIE0_LOCKED (1 << 0)
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#define PLAT_PCIE_STATUS_PCIE1_LOCKED (1 << 8)
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#define PLAT_PCIE_STATUS_PCIE2_LOCKED (1 << 16)
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PLAT_FLASH_CTL = 0x1c,
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PLAT_SPARE0 = 0x20,
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PLAT_SPARE1 = 0x24,
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PLAT_SPARE2 = 0x28,
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PLAT_SPARE3 = 0x2c,
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PLAT_MMCM_DIV = 0x30,
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#define PLAT_MMCM_DIV_CLK0DIV_SHIFT 0
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#define PLAT_MMCM_DIV_INPUT_SHIFT 8
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#define PLAT_MMCM_DIV_MUL_SHIFT 16
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#define PLAT_MMCM_DIV_CLK1DIV_SHIFT 24
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PLAT_BUILD_CFG = 0x34,
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#define PLAT_BUILD_CFG_IOCU_EN (1 << 0)
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#define PLAT_BUILD_CFG_PCIE0_EN (1 << 1)
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#define PLAT_BUILD_CFG_PCIE1_EN (1 << 2)
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#define PLAT_BUILD_CFG_PCIE2_EN (1 << 3)
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PLAT_DDR_CFG = 0x38,
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#define PLAT_DDR_CFG_SIZE (0xf << 0)
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#define PLAT_DDR_CFG_MHZ (0xfff << 4)
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PLAT_NOC_PCIE0_ADDR = 0x3c,
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PLAT_NOC_PCIE1_ADDR = 0x40,
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PLAT_NOC_PCIE2_ADDR = 0x44,
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PLAT_SYS_CTL = 0x48,
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};
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static void boston_lcd_event(void *opaque, QEMUChrEvent event)
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{
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BostonState *s = opaque;
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if (event == CHR_EVENT_OPENED && !s->lcd_inited) {
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qemu_chr_fe_printf(&s->lcd_display, " ");
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s->lcd_inited = true;
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}
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}
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static uint64_t boston_lcd_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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BostonState *s = opaque;
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uint64_t val = 0;
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switch (size) {
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case 8:
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val |= (uint64_t)s->lcd_content[(addr + 7) & 0x7] << 56;
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val |= (uint64_t)s->lcd_content[(addr + 6) & 0x7] << 48;
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val |= (uint64_t)s->lcd_content[(addr + 5) & 0x7] << 40;
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val |= (uint64_t)s->lcd_content[(addr + 4) & 0x7] << 32;
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/* fall through */
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case 4:
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val |= (uint64_t)s->lcd_content[(addr + 3) & 0x7] << 24;
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val |= (uint64_t)s->lcd_content[(addr + 2) & 0x7] << 16;
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/* fall through */
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case 2:
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val |= (uint64_t)s->lcd_content[(addr + 1) & 0x7] << 8;
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/* fall through */
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case 1:
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val |= (uint64_t)s->lcd_content[(addr + 0) & 0x7];
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break;
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}
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return val;
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}
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static void boston_lcd_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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BostonState *s = opaque;
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switch (size) {
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case 8:
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s->lcd_content[(addr + 7) & 0x7] = val >> 56;
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s->lcd_content[(addr + 6) & 0x7] = val >> 48;
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s->lcd_content[(addr + 5) & 0x7] = val >> 40;
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s->lcd_content[(addr + 4) & 0x7] = val >> 32;
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/* fall through */
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case 4:
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s->lcd_content[(addr + 3) & 0x7] = val >> 24;
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s->lcd_content[(addr + 2) & 0x7] = val >> 16;
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/* fall through */
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case 2:
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s->lcd_content[(addr + 1) & 0x7] = val >> 8;
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/* fall through */
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case 1:
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s->lcd_content[(addr + 0) & 0x7] = val;
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break;
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}
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qemu_chr_fe_printf(&s->lcd_display,
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"\r%-8.8s", s->lcd_content);
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}
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static const MemoryRegionOps boston_lcd_ops = {
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.read = boston_lcd_read,
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.write = boston_lcd_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static uint64_t boston_platreg_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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BostonState *s = opaque;
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uint32_t gic_freq, val;
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if (size != 4) {
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qemu_log_mask(LOG_UNIMP, "%uB platform register read\n", size);
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return 0;
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}
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switch (addr & 0xffff) {
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case PLAT_FPGA_BUILD:
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case PLAT_CORE_CL:
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case PLAT_WRAPPER_CL:
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return 0;
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case PLAT_DDR3_STATUS:
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return PLAT_DDR3_STATUS_LOCKED | PLAT_DDR3_STATUS_CALIBRATED;
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case PLAT_MMCM_DIV:
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gic_freq = mips_gictimer_get_freq(s->cps.gic.gic_timer) / 1000000;
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val = gic_freq << PLAT_MMCM_DIV_INPUT_SHIFT;
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val |= 1 << PLAT_MMCM_DIV_MUL_SHIFT;
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val |= 1 << PLAT_MMCM_DIV_CLK0DIV_SHIFT;
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val |= 1 << PLAT_MMCM_DIV_CLK1DIV_SHIFT;
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return val;
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case PLAT_BUILD_CFG:
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val = PLAT_BUILD_CFG_PCIE0_EN;
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val |= PLAT_BUILD_CFG_PCIE1_EN;
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val |= PLAT_BUILD_CFG_PCIE2_EN;
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return val;
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case PLAT_DDR_CFG:
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val = s->mach->ram_size / GiB;
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assert(!(val & ~PLAT_DDR_CFG_SIZE));
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val |= PLAT_DDR_CFG_MHZ;
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return val;
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default:
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qemu_log_mask(LOG_UNIMP, "Read platform register 0x%" HWADDR_PRIx "\n",
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addr & 0xffff);
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return 0;
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}
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}
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static void boston_platreg_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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if (size != 4) {
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qemu_log_mask(LOG_UNIMP, "%uB platform register write\n", size);
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return;
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}
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switch (addr & 0xffff) {
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case PLAT_FPGA_BUILD:
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case PLAT_CORE_CL:
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case PLAT_WRAPPER_CL:
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case PLAT_DDR3_STATUS:
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case PLAT_PCIE_STATUS:
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case PLAT_MMCM_DIV:
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case PLAT_BUILD_CFG:
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case PLAT_DDR_CFG:
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/* read only */
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break;
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case PLAT_SOFTRST_CTL:
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if (val & PLAT_SOFTRST_CTL_SYSRESET) {
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qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
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}
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "Write platform register 0x%" HWADDR_PRIx
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" = 0x%" PRIx64 "\n", addr & 0xffff, val);
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break;
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}
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}
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static const MemoryRegionOps boston_platreg_ops = {
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.read = boston_platreg_read,
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.write = boston_platreg_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static const TypeInfo boston_device = {
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.name = TYPE_MIPS_BOSTON,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(BostonState),
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};
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static void boston_register_types(void)
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{
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type_register_static(&boston_device);
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}
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type_init(boston_register_types)
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static void gen_firmware(uint32_t *p, hwaddr kernel_entry, hwaddr fdt_addr,
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bool is_64b)
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{
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const uint32_t cm_base = 0x16100000;
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const uint32_t gic_base = 0x16120000;
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const uint32_t cpc_base = 0x16200000;
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/* Move CM GCRs */
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if (is_64b) {
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stl_p(p++, 0x40287803); /* dmfc0 $8, CMGCRBase */
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stl_p(p++, 0x00084138); /* dsll $8, $8, 4 */
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} else {
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stl_p(p++, 0x40087803); /* mfc0 $8, CMGCRBase */
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stl_p(p++, 0x00084100); /* sll $8, $8, 4 */
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}
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stl_p(p++, 0x3c09a000); /* lui $9, 0xa000 */
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stl_p(p++, 0x01094025); /* or $8, $9 */
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stl_p(p++, 0x3c0a0000 | (cm_base >> 16)); /* lui $10, cm_base >> 16 */
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if (is_64b) {
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stl_p(p++, 0xfd0a0008); /* sd $10, 0x8($8) */
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} else {
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stl_p(p++, 0xad0a0008); /* sw $10, 0x8($8) */
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}
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stl_p(p++, 0x012a4025); /* or $8, $10 */
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/* Move & enable GIC GCRs */
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stl_p(p++, 0x3c090000 | (gic_base >> 16)); /* lui $9, gic_base >> 16 */
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stl_p(p++, 0x35290001); /* ori $9, 0x1 */
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if (is_64b) {
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stl_p(p++, 0xfd090080); /* sd $9, 0x80($8) */
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} else {
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stl_p(p++, 0xad090080); /* sw $9, 0x80($8) */
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}
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/* Move & enable CPC GCRs */
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stl_p(p++, 0x3c090000 | (cpc_base >> 16)); /* lui $9, cpc_base >> 16 */
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stl_p(p++, 0x35290001); /* ori $9, 0x1 */
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if (is_64b) {
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stl_p(p++, 0xfd090088); /* sd $9, 0x88($8) */
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} else {
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stl_p(p++, 0xad090088); /* sw $9, 0x88($8) */
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}
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/*
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* Setup argument registers to follow the UHI boot protocol:
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*
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* a0/$4 = -2
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* a1/$5 = virtual address of FDT
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* a2/$6 = 0
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* a3/$7 = 0
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*/
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stl_p(p++, 0x2404fffe); /* li $4, -2 */
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/* lui $5, hi(fdt_addr) */
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stl_p(p++, 0x3c050000 | ((fdt_addr >> 16) & 0xffff));
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if (fdt_addr & 0xffff) { /* ori $5, lo(fdt_addr) */
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stl_p(p++, 0x34a50000 | (fdt_addr & 0xffff));
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}
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stl_p(p++, 0x34060000); /* li $6, 0 */
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stl_p(p++, 0x34070000); /* li $7, 0 */
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/* Load kernel entry address & jump to it */
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/* lui $25, hi(kernel_entry) */
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stl_p(p++, 0x3c190000 | ((kernel_entry >> 16) & 0xffff));
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/* ori $25, lo(kernel_entry) */
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stl_p(p++, 0x37390000 | (kernel_entry & 0xffff));
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stl_p(p++, 0x03200009); /* jr $25 */
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}
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static const void *boston_fdt_filter(void *opaque, const void *fdt_orig,
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const void *match_data, hwaddr *load_addr)
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{
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BostonState *s = BOSTON(opaque);
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|
MachineState *machine = s->mach;
|
||
|
|
const char *cmdline;
|
||
|
|
int err;
|
||
|
|
void *fdt;
|
||
|
|
size_t fdt_sz, ram_low_sz, ram_high_sz;
|
||
|
|
|
||
|
|
fdt_sz = fdt_totalsize(fdt_orig) * 2;
|
||
|
|
fdt = g_malloc0(fdt_sz);
|
||
|
|
|
||
|
|
err = fdt_open_into(fdt_orig, fdt, fdt_sz);
|
||
|
|
if (err) {
|
||
|
|
fprintf(stderr, "unable to open FDT\n");
|
||
|
|
return NULL;
|
||
|
|
}
|
||
|
|
|
||
|
|
cmdline = (machine->kernel_cmdline && machine->kernel_cmdline[0])
|
||
|
|
? machine->kernel_cmdline : " ";
|
||
|
|
err = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
|
||
|
|
if (err < 0) {
|
||
|
|
fprintf(stderr, "couldn't set /chosen/bootargs\n");
|
||
|
|
return NULL;
|
||
|
|
}
|
||
|
|
|
||
|
|
ram_low_sz = MIN(256 * MiB, machine->ram_size);
|
||
|
|
ram_high_sz = machine->ram_size - ram_low_sz;
|
||
|
|
qemu_fdt_setprop_sized_cells(fdt, "/memory@0", "reg",
|
||
|
|
1, 0x00000000, 1, ram_low_sz,
|
||
|
|
1, 0x90000000, 1, ram_high_sz);
|
||
|
|
|
||
|
|
fdt = g_realloc(fdt, fdt_totalsize(fdt));
|
||
|
|
qemu_fdt_dumpdtb(fdt, fdt_sz);
|
||
|
|
|
||
|
|
s->fdt_base = *load_addr;
|
||
|
|
|
||
|
|
return fdt;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const void *boston_kernel_filter(void *opaque, const void *kernel,
|
||
|
|
hwaddr *load_addr, hwaddr *entry_addr)
|
||
|
|
{
|
||
|
|
BostonState *s = BOSTON(opaque);
|
||
|
|
|
||
|
|
s->kernel_entry = *entry_addr;
|
||
|
|
|
||
|
|
return kernel;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct fit_loader_match boston_matches[] = {
|
||
|
|
{ "img,boston" },
|
||
|
|
{ NULL },
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct fit_loader boston_fit_loader = {
|
||
|
|
.matches = boston_matches,
|
||
|
|
.addr_to_phys = cpu_mips_kseg0_to_phys,
|
||
|
|
.fdt_filter = boston_fdt_filter,
|
||
|
|
.kernel_filter = boston_kernel_filter,
|
||
|
|
};
|
||
|
|
|
||
|
|
static inline XilinxPCIEHost *
|
||
|
|
xilinx_pcie_init(MemoryRegion *sys_mem, uint32_t bus_nr,
|
||
|
|
hwaddr cfg_base, uint64_t cfg_size,
|
||
|
|
hwaddr mmio_base, uint64_t mmio_size,
|
||
|
|
qemu_irq irq, bool link_up)
|
||
|
|
{
|
||
|
|
DeviceState *dev;
|
||
|
|
MemoryRegion *cfg, *mmio;
|
||
|
|
|
||
|
|
dev = qdev_new(TYPE_XILINX_PCIE_HOST);
|
||
|
|
|
||
|
|
qdev_prop_set_uint32(dev, "bus_nr", bus_nr);
|
||
|
|
qdev_prop_set_uint64(dev, "cfg_base", cfg_base);
|
||
|
|
qdev_prop_set_uint64(dev, "cfg_size", cfg_size);
|
||
|
|
qdev_prop_set_uint64(dev, "mmio_base", mmio_base);
|
||
|
|
qdev_prop_set_uint64(dev, "mmio_size", mmio_size);
|
||
|
|
qdev_prop_set_bit(dev, "link_up", link_up);
|
||
|
|
|
||
|
|
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
|
||
|
|
|
||
|
|
cfg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
|
||
|
|
memory_region_add_subregion_overlap(sys_mem, cfg_base, cfg, 0);
|
||
|
|
|
||
|
|
mmio = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
|
||
|
|
memory_region_add_subregion_overlap(sys_mem, 0, mmio, 0);
|
||
|
|
|
||
|
|
qdev_connect_gpio_out_named(dev, "interrupt_out", 0, irq);
|
||
|
|
|
||
|
|
return XILINX_PCIE_HOST(dev);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void boston_mach_init(MachineState *machine)
|
||
|
|
{
|
||
|
|
DeviceState *dev;
|
||
|
|
BostonState *s;
|
||
|
|
MemoryRegion *flash, *ddr_low_alias, *lcd, *platreg;
|
||
|
|
MemoryRegion *sys_mem = get_system_memory();
|
||
|
|
XilinxPCIEHost *pcie2;
|
||
|
|
PCIDevice *ahci;
|
||
|
|
DriveInfo *hd[6];
|
||
|
|
Chardev *chr;
|
||
|
|
int fw_size, fit_err;
|
||
|
|
bool is_64b;
|
||
|
|
|
||
|
|
if ((machine->ram_size % GiB) ||
|
||
|
|
(machine->ram_size > (2 * GiB))) {
|
||
|
|
error_report("Memory size must be 1GB or 2GB");
|
||
|
|
exit(1);
|
||
|
|
}
|
||
|
|
|
||
|
|
dev = qdev_new(TYPE_MIPS_BOSTON);
|
||
|
|
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
|
||
|
|
|
||
|
|
s = BOSTON(dev);
|
||
|
|
s->mach = machine;
|
||
|
|
|
||
|
|
if (!cpu_supports_cps_smp(machine->cpu_type)) {
|
||
|
|
error_report("Boston requires CPUs which support CPS");
|
||
|
|
exit(1);
|
||
|
|
}
|
||
|
|
|
||
|
|
is_64b = cpu_supports_isa(machine->cpu_type, ISA_MIPS64);
|
||
|
|
|
||
|
|
object_initialize_child(OBJECT(machine), "cps", &s->cps, TYPE_MIPS_CPS);
|
||
|
|
object_property_set_str(OBJECT(&s->cps), "cpu-type", machine->cpu_type,
|
||
|
|
&error_fatal);
|
||
|
|
object_property_set_int(OBJECT(&s->cps), "num-vp", machine->smp.cpus,
|
||
|
|
&error_fatal);
|
||
|
|
sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal);
|
||
|
|
|
||
|
|
sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1);
|
||
|
|
|
||
|
|
flash = g_new(MemoryRegion, 1);
|
||
|
|
memory_region_init_rom(flash, NULL, "boston.flash", 128 * MiB,
|
||
|
|
&error_fatal);
|
||
|
|
memory_region_add_subregion_overlap(sys_mem, 0x18000000, flash, 0);
|
||
|
|
|
||
|
|
memory_region_add_subregion_overlap(sys_mem, 0x80000000, machine->ram, 0);
|
||
|
|
|
||
|
|
ddr_low_alias = g_new(MemoryRegion, 1);
|
||
|
|
memory_region_init_alias(ddr_low_alias, NULL, "boston_low.ddr",
|
||
|
|
machine->ram, 0,
|
||
|
|
MIN(machine->ram_size, (256 * MiB)));
|
||
|
|
memory_region_add_subregion_overlap(sys_mem, 0, ddr_low_alias, 0);
|
||
|
|
|
||
|
|
xilinx_pcie_init(sys_mem, 0,
|
||
|
|
0x10000000, 32 * MiB,
|
||
|
|
0x40000000, 1 * GiB,
|
||
|
|
get_cps_irq(&s->cps, 2), false);
|
||
|
|
|
||
|
|
xilinx_pcie_init(sys_mem, 1,
|
||
|
|
0x12000000, 32 * MiB,
|
||
|
|
0x20000000, 512 * MiB,
|
||
|
|
get_cps_irq(&s->cps, 1), false);
|
||
|
|
|
||
|
|
pcie2 = xilinx_pcie_init(sys_mem, 2,
|
||
|
|
0x14000000, 32 * MiB,
|
||
|
|
0x16000000, 1 * MiB,
|
||
|
|
get_cps_irq(&s->cps, 0), true);
|
||
|
|
|
||
|
|
platreg = g_new(MemoryRegion, 1);
|
||
|
|
memory_region_init_io(platreg, NULL, &boston_platreg_ops, s,
|
||
|
|
"boston-platregs", 0x1000);
|
||
|
|
memory_region_add_subregion_overlap(sys_mem, 0x17ffd000, platreg, 0);
|
||
|
|
|
||
|
|
s->uart = serial_mm_init(sys_mem, 0x17ffe000, 2,
|
||
|
|
get_cps_irq(&s->cps, 3), 10000000,
|
||
|
|
serial_hd(0), DEVICE_NATIVE_ENDIAN);
|
||
|
|
|
||
|
|
lcd = g_new(MemoryRegion, 1);
|
||
|
|
memory_region_init_io(lcd, NULL, &boston_lcd_ops, s, "boston-lcd", 0x8);
|
||
|
|
memory_region_add_subregion_overlap(sys_mem, 0x17fff000, lcd, 0);
|
||
|
|
|
||
|
|
chr = qemu_chr_new("lcd", "vc:320x240", NULL);
|
||
|
|
qemu_chr_fe_init(&s->lcd_display, chr, NULL);
|
||
|
|
qemu_chr_fe_set_handlers(&s->lcd_display, NULL, NULL,
|
||
|
|
boston_lcd_event, NULL, s, NULL, true);
|
||
|
|
|
||
|
|
ahci = pci_create_simple_multifunction(&PCI_BRIDGE(&pcie2->root)->sec_bus,
|
||
|
|
PCI_DEVFN(0, 0),
|
||
|
|
true, TYPE_ICH9_AHCI);
|
||
|
|
g_assert(ARRAY_SIZE(hd) == ahci_get_num_ports(ahci));
|
||
|
|
ide_drive_get(hd, ahci_get_num_ports(ahci));
|
||
|
|
ahci_ide_create_devs(ahci, hd);
|
||
|
|
|
||
|
|
if (machine->firmware) {
|
||
|
|
fw_size = load_image_targphys(machine->firmware,
|
||
|
|
0x1fc00000, 4 * MiB);
|
||
|
|
if (fw_size == -1) {
|
||
|
|
error_report("unable to load firmware image '%s'",
|
||
|
|
machine->firmware);
|
||
|
|
exit(1);
|
||
|
|
}
|
||
|
|
} else if (machine->kernel_filename) {
|
||
|
|
fit_err = load_fit(&boston_fit_loader, machine->kernel_filename, s);
|
||
|
|
if (fit_err) {
|
||
|
|
error_report("unable to load FIT image");
|
||
|
|
exit(1);
|
||
|
|
}
|
||
|
|
|
||
|
|
gen_firmware(memory_region_get_ram_ptr(flash) + 0x7c00000,
|
||
|
|
s->kernel_entry, s->fdt_base, is_64b);
|
||
|
|
} else if (!qtest_enabled()) {
|
||
|
|
error_report("Please provide either a -kernel or -bios argument");
|
||
|
|
exit(1);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static void boston_mach_class_init(MachineClass *mc)
|
||
|
|
{
|
||
|
|
mc->desc = "MIPS Boston";
|
||
|
|
mc->init = boston_mach_init;
|
||
|
|
mc->block_default_type = IF_IDE;
|
||
|
|
mc->default_ram_size = 1 * GiB;
|
||
|
|
mc->default_ram_id = "boston.ddr";
|
||
|
|
mc->max_cpus = 16;
|
||
|
|
mc->default_cpu_type = MIPS_CPU_TYPE_NAME("I6400");
|
||
|
|
}
|
||
|
|
|
||
|
|
DEFINE_MACHINE("boston", boston_mach_class_init)
|