320 lines
9.6 KiB
C
320 lines
9.6 KiB
C
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/*
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* ARM MPS2 AN505 FPGAIO emulation
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*
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* Copyright (c) 2018 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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/* This is a model of the "FPGA system control and I/O" block found
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* in the AN505 FPGA image for the MPS2 devboard.
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* It is documented in AN505:
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* http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "qapi/error.h"
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#include "trace.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "hw/registerfields.h"
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#include "hw/misc/mps2-fpgaio.h"
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#include "hw/qdev-properties.h"
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#include "qemu/timer.h"
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REG32(LED0, 0)
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REG32(BUTTON, 8)
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REG32(CLK1HZ, 0x10)
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REG32(CLK100HZ, 0x14)
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REG32(COUNTER, 0x18)
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REG32(PRESCALE, 0x1c)
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REG32(PSCNTR, 0x20)
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REG32(MISC, 0x4c)
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static uint32_t counter_from_tickoff(int64_t now, int64_t tick_offset, int frq)
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{
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return muldiv64(now - tick_offset, frq, NANOSECONDS_PER_SECOND);
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}
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static int64_t tickoff_from_counter(int64_t now, uint32_t count, int frq)
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{
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return now - muldiv64(count, NANOSECONDS_PER_SECOND, frq);
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}
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static void resync_counter(MPS2FPGAIO *s)
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{
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/*
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* Update s->counter and s->pscntr to their true current values
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* by calculating how many times PSCNTR has ticked since the
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* last time we did a resync.
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*/
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int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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int64_t elapsed = now - s->pscntr_sync_ticks;
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/*
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* Round elapsed down to a whole number of PSCNTR ticks, so we don't
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* lose time if we do multiple resyncs in a single tick.
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*/
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uint64_t ticks = muldiv64(elapsed, s->prescale_clk, NANOSECONDS_PER_SECOND);
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/*
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* Work out what PSCNTR and COUNTER have moved to. We assume that
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* PSCNTR reloads from PRESCALE one tick-period after it hits zero,
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* and that COUNTER increments at the same moment.
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*/
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if (ticks == 0) {
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/* We haven't ticked since the last time we were asked */
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return;
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} else if (ticks < s->pscntr) {
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/* We haven't yet reached zero, just reduce the PSCNTR */
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s->pscntr -= ticks;
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} else {
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if (s->prescale == 0) {
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/*
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* If the reload value is zero then the PSCNTR will stick
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* at zero once it reaches it, and so we will increment
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* COUNTER every tick after that.
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*/
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s->counter += ticks - s->pscntr;
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s->pscntr = 0;
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} else {
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/*
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* This is the complicated bit. This ASCII art diagram gives an
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* example with PRESCALE==5 PSCNTR==7:
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*
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* ticks 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
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* PSCNTR 7 6 5 4 3 2 1 0 5 4 3 2 1 0 5
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* cinc 1 2
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* y 0 1 2 3 4 5 6 7 8 9 10 11 12
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* x 0 1 2 3 4 5 0 1 2 3 4 5 0
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*
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* where x = y % (s->prescale + 1)
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* and so PSCNTR = s->prescale - x
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* and COUNTER is incremented by y / (s->prescale + 1)
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*
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* The case where PSCNTR < PRESCALE works out the same,
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* though we must be careful to calculate y as 64-bit unsigned
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* for all parts of the expression.
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* y < 0 is not possible because that implies ticks < s->pscntr.
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*/
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uint64_t y = ticks - s->pscntr + s->prescale;
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s->pscntr = s->prescale - (y % (s->prescale + 1));
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s->counter += y / (s->prescale + 1);
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}
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}
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/*
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* Only advance the sync time to the timestamp of the last PSCNTR tick,
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* not all the way to 'now', so we don't lose time if we do multiple
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* resyncs in a single tick.
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*/
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s->pscntr_sync_ticks += muldiv64(ticks, NANOSECONDS_PER_SECOND,
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s->prescale_clk);
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}
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static uint64_t mps2_fpgaio_read(void *opaque, hwaddr offset, unsigned size)
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{
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MPS2FPGAIO *s = MPS2_FPGAIO(opaque);
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uint64_t r;
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int64_t now;
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switch (offset) {
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case A_LED0:
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r = s->led0;
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break;
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case A_BUTTON:
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/* User-pressable board buttons. We don't model that, so just return
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* zeroes.
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*/
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r = 0;
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break;
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case A_PRESCALE:
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r = s->prescale;
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break;
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case A_MISC:
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r = s->misc;
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break;
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case A_CLK1HZ:
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now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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r = counter_from_tickoff(now, s->clk1hz_tick_offset, 1);
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break;
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case A_CLK100HZ:
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now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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r = counter_from_tickoff(now, s->clk100hz_tick_offset, 100);
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break;
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case A_COUNTER:
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resync_counter(s);
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r = s->counter;
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break;
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case A_PSCNTR:
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resync_counter(s);
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r = s->pscntr;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"MPS2 FPGAIO read: bad offset %x\n", (int) offset);
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r = 0;
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break;
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}
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trace_mps2_fpgaio_read(offset, r, size);
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return r;
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}
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static void mps2_fpgaio_write(void *opaque, hwaddr offset, uint64_t value,
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unsigned size)
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{
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MPS2FPGAIO *s = MPS2_FPGAIO(opaque);
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int64_t now;
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trace_mps2_fpgaio_write(offset, value, size);
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switch (offset) {
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case A_LED0:
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/* LED bits [1:0] control board LEDs. We don't currently have
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* a mechanism for displaying this graphically, so use a trace event.
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*/
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trace_mps2_fpgaio_leds(value & 0x02 ? '*' : '.',
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value & 0x01 ? '*' : '.');
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s->led0 = value & 0x3;
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break;
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case A_PRESCALE:
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resync_counter(s);
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s->prescale = value;
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break;
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case A_MISC:
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/* These are control bits for some of the other devices on the
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* board (SPI, CLCD, etc). We don't implement that yet, so just
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* make the bits read as written.
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*/
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qemu_log_mask(LOG_UNIMP,
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"MPS2 FPGAIO: MISC control bits unimplemented\n");
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s->misc = value;
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break;
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case A_CLK1HZ:
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now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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s->clk1hz_tick_offset = tickoff_from_counter(now, value, 1);
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break;
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case A_CLK100HZ:
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now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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s->clk100hz_tick_offset = tickoff_from_counter(now, value, 100);
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break;
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case A_COUNTER:
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resync_counter(s);
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s->counter = value;
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break;
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case A_PSCNTR:
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resync_counter(s);
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s->pscntr = value;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"MPS2 FPGAIO write: bad offset 0x%x\n", (int) offset);
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break;
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}
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}
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static const MemoryRegionOps mps2_fpgaio_ops = {
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.read = mps2_fpgaio_read,
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.write = mps2_fpgaio_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void mps2_fpgaio_reset(DeviceState *dev)
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{
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MPS2FPGAIO *s = MPS2_FPGAIO(dev);
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int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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trace_mps2_fpgaio_reset();
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s->led0 = 0;
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s->prescale = 0;
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s->misc = 0;
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s->clk1hz_tick_offset = tickoff_from_counter(now, 0, 1);
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s->clk100hz_tick_offset = tickoff_from_counter(now, 0, 100);
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s->counter = 0;
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s->pscntr = 0;
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s->pscntr_sync_ticks = now;
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}
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static void mps2_fpgaio_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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MPS2FPGAIO *s = MPS2_FPGAIO(obj);
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memory_region_init_io(&s->iomem, obj, &mps2_fpgaio_ops, s,
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"mps2-fpgaio", 0x1000);
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sysbus_init_mmio(sbd, &s->iomem);
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}
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static bool mps2_fpgaio_counters_needed(void *opaque)
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{
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/* Currently vmstate.c insists all subsections have a 'needed' function */
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return true;
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}
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static const VMStateDescription mps2_fpgaio_counters_vmstate = {
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.name = "mps2-fpgaio/counters",
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.version_id = 2,
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.minimum_version_id = 2,
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.needed = mps2_fpgaio_counters_needed,
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.fields = (VMStateField[]) {
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VMSTATE_INT64(clk1hz_tick_offset, MPS2FPGAIO),
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VMSTATE_INT64(clk100hz_tick_offset, MPS2FPGAIO),
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VMSTATE_UINT32(counter, MPS2FPGAIO),
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VMSTATE_UINT32(pscntr, MPS2FPGAIO),
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VMSTATE_INT64(pscntr_sync_ticks, MPS2FPGAIO),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription mps2_fpgaio_vmstate = {
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.name = "mps2-fpgaio",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(led0, MPS2FPGAIO),
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VMSTATE_UINT32(prescale, MPS2FPGAIO),
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VMSTATE_UINT32(misc, MPS2FPGAIO),
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VMSTATE_END_OF_LIST()
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},
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.subsections = (const VMStateDescription*[]) {
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&mps2_fpgaio_counters_vmstate,
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NULL
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}
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};
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static Property mps2_fpgaio_properties[] = {
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/* Frequency of the prescale counter */
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DEFINE_PROP_UINT32("prescale-clk", MPS2FPGAIO, prescale_clk, 20000000),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void mps2_fpgaio_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->vmsd = &mps2_fpgaio_vmstate;
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dc->reset = mps2_fpgaio_reset;
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device_class_set_props(dc, mps2_fpgaio_properties);
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}
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static const TypeInfo mps2_fpgaio_info = {
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.name = TYPE_MPS2_FPGAIO,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(MPS2FPGAIO),
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.instance_init = mps2_fpgaio_init,
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.class_init = mps2_fpgaio_class_init,
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};
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static void mps2_fpgaio_register_types(void)
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{
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type_register_static(&mps2_fpgaio_info);
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}
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type_init(mps2_fpgaio_register_types);
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