339 lines
9.1 KiB
C
339 lines
9.1 KiB
C
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/*
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* ARM TrustZone peripheral protection controller emulation
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*
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* Copyright (c) 2018 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "qapi/error.h"
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#include "trace.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "hw/registerfields.h"
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#include "hw/irq.h"
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#include "hw/misc/tz-ppc.h"
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#include "hw/qdev-properties.h"
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static void tz_ppc_update_irq(TZPPC *s)
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{
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bool level = s->irq_status && s->irq_enable;
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trace_tz_ppc_update_irq(level);
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qemu_set_irq(s->irq, level);
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}
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static void tz_ppc_cfg_nonsec(void *opaque, int n, int level)
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{
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TZPPC *s = TZ_PPC(opaque);
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assert(n < TZ_NUM_PORTS);
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trace_tz_ppc_cfg_nonsec(n, level);
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s->cfg_nonsec[n] = level;
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}
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static void tz_ppc_cfg_ap(void *opaque, int n, int level)
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{
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TZPPC *s = TZ_PPC(opaque);
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assert(n < TZ_NUM_PORTS);
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trace_tz_ppc_cfg_ap(n, level);
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s->cfg_ap[n] = level;
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}
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static void tz_ppc_cfg_sec_resp(void *opaque, int n, int level)
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{
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TZPPC *s = TZ_PPC(opaque);
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trace_tz_ppc_cfg_sec_resp(level);
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s->cfg_sec_resp = level;
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}
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static void tz_ppc_irq_enable(void *opaque, int n, int level)
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{
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TZPPC *s = TZ_PPC(opaque);
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trace_tz_ppc_irq_enable(level);
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s->irq_enable = level;
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tz_ppc_update_irq(s);
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}
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static void tz_ppc_irq_clear(void *opaque, int n, int level)
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{
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TZPPC *s = TZ_PPC(opaque);
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trace_tz_ppc_irq_clear(level);
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s->irq_clear = level;
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if (level) {
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s->irq_status = false;
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tz_ppc_update_irq(s);
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}
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}
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static bool tz_ppc_check(TZPPC *s, int n, MemTxAttrs attrs)
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{
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/* Check whether to allow an access to port n; return true if
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* the check passes, and false if the transaction must be blocked.
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* If the latter, the caller must check cfg_sec_resp to determine
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* whether to abort or RAZ/WI the transaction.
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* The checks are:
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* + nonsec_mask suppresses any check of the secure attribute
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* + otherwise, block if cfg_nonsec is 1 and transaction is secure,
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* or if cfg_nonsec is 0 and transaction is non-secure
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* + block if transaction is usermode and cfg_ap is 0
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*/
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if ((attrs.secure == s->cfg_nonsec[n] && !(s->nonsec_mask & (1 << n))) ||
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(attrs.user && !s->cfg_ap[n])) {
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/* Block the transaction. */
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if (!s->irq_clear) {
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/* Note that holding irq_clear high suppresses interrupts */
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s->irq_status = true;
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tz_ppc_update_irq(s);
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}
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return false;
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}
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return true;
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}
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static MemTxResult tz_ppc_read(void *opaque, hwaddr addr, uint64_t *pdata,
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unsigned size, MemTxAttrs attrs)
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{
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TZPPCPort *p = opaque;
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TZPPC *s = p->ppc;
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int n = p - s->port;
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AddressSpace *as = &p->downstream_as;
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uint64_t data;
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MemTxResult res;
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if (!tz_ppc_check(s, n, attrs)) {
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trace_tz_ppc_read_blocked(n, addr, attrs.secure, attrs.user);
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if (s->cfg_sec_resp) {
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return MEMTX_ERROR;
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} else {
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*pdata = 0;
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return MEMTX_OK;
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}
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}
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switch (size) {
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case 1:
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data = address_space_ldub(as, addr, attrs, &res);
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break;
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case 2:
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data = address_space_lduw_le(as, addr, attrs, &res);
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break;
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case 4:
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data = address_space_ldl_le(as, addr, attrs, &res);
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break;
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case 8:
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data = address_space_ldq_le(as, addr, attrs, &res);
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break;
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default:
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g_assert_not_reached();
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}
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*pdata = data;
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return res;
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}
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static MemTxResult tz_ppc_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned size, MemTxAttrs attrs)
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{
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TZPPCPort *p = opaque;
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TZPPC *s = p->ppc;
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AddressSpace *as = &p->downstream_as;
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int n = p - s->port;
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MemTxResult res;
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if (!tz_ppc_check(s, n, attrs)) {
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trace_tz_ppc_write_blocked(n, addr, attrs.secure, attrs.user);
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if (s->cfg_sec_resp) {
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return MEMTX_ERROR;
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} else {
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return MEMTX_OK;
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}
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}
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switch (size) {
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case 1:
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address_space_stb(as, addr, val, attrs, &res);
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break;
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case 2:
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address_space_stw_le(as, addr, val, attrs, &res);
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break;
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case 4:
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address_space_stl_le(as, addr, val, attrs, &res);
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break;
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case 8:
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address_space_stq_le(as, addr, val, attrs, &res);
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break;
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default:
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g_assert_not_reached();
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}
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return res;
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}
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static const MemoryRegionOps tz_ppc_ops = {
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.read_with_attrs = tz_ppc_read,
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.write_with_attrs = tz_ppc_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static bool tz_ppc_dummy_accepts(void *opaque, hwaddr addr,
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unsigned size, bool is_write,
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MemTxAttrs attrs)
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{
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/*
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* Board code should never map the upstream end of an unused port,
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* so we should never try to make a memory access to it.
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*/
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g_assert_not_reached();
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}
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static const MemoryRegionOps tz_ppc_dummy_ops = {
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.valid.accepts = tz_ppc_dummy_accepts,
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};
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static void tz_ppc_reset(DeviceState *dev)
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{
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TZPPC *s = TZ_PPC(dev);
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trace_tz_ppc_reset();
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s->cfg_sec_resp = false;
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memset(s->cfg_nonsec, 0, sizeof(s->cfg_nonsec));
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memset(s->cfg_ap, 0, sizeof(s->cfg_ap));
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}
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static void tz_ppc_init(Object *obj)
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{
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DeviceState *dev = DEVICE(obj);
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TZPPC *s = TZ_PPC(obj);
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qdev_init_gpio_in_named(dev, tz_ppc_cfg_nonsec, "cfg_nonsec", TZ_NUM_PORTS);
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qdev_init_gpio_in_named(dev, tz_ppc_cfg_ap, "cfg_ap", TZ_NUM_PORTS);
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qdev_init_gpio_in_named(dev, tz_ppc_cfg_sec_resp, "cfg_sec_resp", 1);
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qdev_init_gpio_in_named(dev, tz_ppc_irq_enable, "irq_enable", 1);
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qdev_init_gpio_in_named(dev, tz_ppc_irq_clear, "irq_clear", 1);
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qdev_init_gpio_out_named(dev, &s->irq, "irq", 1);
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}
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static void tz_ppc_realize(DeviceState *dev, Error **errp)
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{
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Object *obj = OBJECT(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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TZPPC *s = TZ_PPC(dev);
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int i;
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int max_port = 0;
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/* We can't create the upstream end of the port until realize,
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* as we don't know the size of the MR used as the downstream until then.
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*/
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for (i = 0; i < TZ_NUM_PORTS; i++) {
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if (s->port[i].downstream) {
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max_port = i;
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}
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}
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for (i = 0; i <= max_port; i++) {
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TZPPCPort *port = &s->port[i];
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char *name;
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uint64_t size;
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if (!port->downstream) {
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/*
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* Create dummy sysbus MMIO region so the sysbus region
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* numbering doesn't get out of sync with the port numbers.
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* The size is entirely arbitrary.
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*/
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name = g_strdup_printf("tz-ppc-dummy-port[%d]", i);
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memory_region_init_io(&port->upstream, obj, &tz_ppc_dummy_ops,
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port, name, 0x10000);
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sysbus_init_mmio(sbd, &port->upstream);
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g_free(name);
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continue;
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}
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name = g_strdup_printf("tz-ppc-port[%d]", i);
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port->ppc = s;
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address_space_init(&port->downstream_as, port->downstream, name);
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size = memory_region_size(port->downstream);
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memory_region_init_io(&port->upstream, obj, &tz_ppc_ops,
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port, name, size);
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sysbus_init_mmio(sbd, &port->upstream);
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g_free(name);
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}
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}
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static const VMStateDescription tz_ppc_vmstate = {
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.name = "tz-ppc",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_BOOL_ARRAY(cfg_nonsec, TZPPC, 16),
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VMSTATE_BOOL_ARRAY(cfg_ap, TZPPC, 16),
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VMSTATE_BOOL(cfg_sec_resp, TZPPC),
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VMSTATE_BOOL(irq_enable, TZPPC),
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VMSTATE_BOOL(irq_clear, TZPPC),
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VMSTATE_BOOL(irq_status, TZPPC),
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VMSTATE_END_OF_LIST()
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}
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};
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#define DEFINE_PORT(N) \
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DEFINE_PROP_LINK("port[" #N "]", TZPPC, port[N].downstream, \
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TYPE_MEMORY_REGION, MemoryRegion *)
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static Property tz_ppc_properties[] = {
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DEFINE_PROP_UINT32("NONSEC_MASK", TZPPC, nonsec_mask, 0),
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DEFINE_PORT(0),
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DEFINE_PORT(1),
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DEFINE_PORT(2),
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DEFINE_PORT(3),
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DEFINE_PORT(4),
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DEFINE_PORT(5),
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DEFINE_PORT(6),
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DEFINE_PORT(7),
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DEFINE_PORT(8),
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DEFINE_PORT(9),
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DEFINE_PORT(10),
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DEFINE_PORT(11),
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DEFINE_PORT(12),
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DEFINE_PORT(13),
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DEFINE_PORT(14),
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DEFINE_PORT(15),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void tz_ppc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = tz_ppc_realize;
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dc->vmsd = &tz_ppc_vmstate;
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dc->reset = tz_ppc_reset;
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device_class_set_props(dc, tz_ppc_properties);
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}
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static const TypeInfo tz_ppc_info = {
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.name = TYPE_TZ_PPC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(TZPPC),
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.instance_init = tz_ppc_init,
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.class_init = tz_ppc_class_init,
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};
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static void tz_ppc_register_types(void)
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{
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type_register_static(&tz_ppc_info);
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}
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type_init(tz_ppc_register_types);
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