464 lines
15 KiB
C
464 lines
15 KiB
C
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/*
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* QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator
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*
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* Copyright (c) 2004-2007 Fabrice Bellard
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "qemu/units.h"
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#include "qapi/error.h"
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#include "hw/ppc/ppc.h"
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#include "hw/qdev-properties.h"
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#include "mac.h"
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#include "hw/input/adb.h"
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#include "sysemu/sysemu.h"
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#include "net/net.h"
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#include "hw/isa/isa.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_host.h"
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#include "hw/boards.h"
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#include "hw/nvram/fw_cfg.h"
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#include "hw/char/escc.h"
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#include "hw/misc/macio/macio.h"
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#include "hw/loader.h"
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#include "hw/fw-path-provider.h"
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#include "elf.h"
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#include "qemu/error-report.h"
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#include "sysemu/kvm.h"
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#include "sysemu/reset.h"
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#include "kvm_ppc.h"
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#include "exec/address-spaces.h"
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#define MAX_IDE_BUS 2
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#define CFG_ADDR 0xf0000510
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#define TBFREQ 16600000UL
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#define CLOCKFREQ 266000000UL
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#define BUSFREQ 66000000UL
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#define NDRV_VGA_FILENAME "qemu_vga.ndrv"
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#define GRACKLE_BASE 0xfec00000
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static void fw_cfg_boot_set(void *opaque, const char *boot_device,
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Error **errp)
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{
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fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
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}
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static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
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{
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return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
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}
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static void ppc_heathrow_reset(void *opaque)
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{
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PowerPCCPU *cpu = opaque;
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cpu_reset(CPU(cpu));
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}
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static void ppc_heathrow_init(MachineState *machine)
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{
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ram_addr_t ram_size = machine->ram_size;
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const char *kernel_filename = machine->kernel_filename;
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const char *kernel_cmdline = machine->kernel_cmdline;
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const char *initrd_filename = machine->initrd_filename;
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const char *boot_device = machine->boot_order;
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MemoryRegion *sysmem = get_system_memory();
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PowerPCCPU *cpu = NULL;
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CPUPPCState *env = NULL;
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char *filename;
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int linux_boot, i;
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MemoryRegion *bios = g_new(MemoryRegion, 1);
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uint32_t kernel_base, initrd_base, cmdline_base = 0;
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int32_t kernel_size, initrd_size;
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PCIBus *pci_bus;
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PCIDevice *macio;
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MACIOIDEState *macio_ide;
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SysBusDevice *s;
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DeviceState *dev, *pic_dev;
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BusState *adb_bus;
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int bios_size;
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unsigned int smp_cpus = machine->smp.cpus;
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uint16_t ppc_boot_device;
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DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
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void *fw_cfg;
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uint64_t tbfreq;
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linux_boot = (kernel_filename != NULL);
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/* init CPUs */
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for (i = 0; i < smp_cpus; i++) {
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cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
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env = &cpu->env;
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/* Set time-base frequency to 16.6 Mhz */
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cpu_ppc_tb_init(env, TBFREQ);
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qemu_register_reset(ppc_heathrow_reset, cpu);
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}
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/* allocate RAM */
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if (ram_size > 2047 * MiB) {
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error_report("Too much memory for this machine: %" PRId64 " MB, "
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"maximum 2047 MB", ram_size / MiB);
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exit(1);
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}
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memory_region_add_subregion(sysmem, 0, machine->ram);
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/* allocate and load BIOS */
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memory_region_init_rom(bios, NULL, "ppc_heathrow.bios", BIOS_SIZE,
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&error_fatal);
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if (bios_name == NULL)
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bios_name = PROM_FILENAME;
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filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
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memory_region_add_subregion(sysmem, PROM_ADDR, bios);
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/* Load OpenBIOS (ELF) */
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if (filename) {
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bios_size = load_elf(filename, NULL, 0, NULL, NULL, NULL, NULL, NULL,
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1, PPC_ELF_MACHINE, 0, 0);
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g_free(filename);
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} else {
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bios_size = -1;
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}
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if (bios_size < 0 || bios_size > BIOS_SIZE) {
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error_report("could not load PowerPC bios '%s'", bios_name);
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exit(1);
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}
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if (linux_boot) {
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uint64_t lowaddr = 0;
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int bswap_needed;
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#ifdef BSWAP_NEEDED
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bswap_needed = 1;
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#else
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bswap_needed = 0;
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#endif
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kernel_base = KERNEL_LOAD_ADDR;
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kernel_size = load_elf(kernel_filename, NULL,
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translate_kernel_address, NULL,
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NULL, &lowaddr, NULL, NULL, 1, PPC_ELF_MACHINE,
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0, 0);
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if (kernel_size < 0)
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kernel_size = load_aout(kernel_filename, kernel_base,
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ram_size - kernel_base, bswap_needed,
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TARGET_PAGE_SIZE);
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if (kernel_size < 0)
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kernel_size = load_image_targphys(kernel_filename,
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kernel_base,
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ram_size - kernel_base);
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if (kernel_size < 0) {
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error_report("could not load kernel '%s'", kernel_filename);
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exit(1);
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}
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/* load initrd */
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if (initrd_filename) {
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initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP);
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initrd_size = load_image_targphys(initrd_filename, initrd_base,
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ram_size - initrd_base);
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if (initrd_size < 0) {
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error_report("could not load initial ram disk '%s'",
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initrd_filename);
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exit(1);
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}
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cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size);
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} else {
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initrd_base = 0;
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initrd_size = 0;
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cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP);
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}
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ppc_boot_device = 'm';
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} else {
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kernel_base = 0;
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kernel_size = 0;
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initrd_base = 0;
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initrd_size = 0;
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ppc_boot_device = '\0';
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for (i = 0; boot_device[i] != '\0'; i++) {
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/* TOFIX: for now, the second IDE channel is not properly
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* used by OHW. The Mac floppy disk are not emulated.
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* For now, OHW cannot boot from the network.
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*/
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#if 0
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if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
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ppc_boot_device = boot_device[i];
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break;
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}
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#else
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if (boot_device[i] >= 'c' && boot_device[i] <= 'd') {
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ppc_boot_device = boot_device[i];
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break;
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}
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#endif
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}
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if (ppc_boot_device == '\0') {
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error_report("No valid boot device for G3 Beige machine");
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exit(1);
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}
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}
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/* XXX: we register only 1 output pin for heathrow PIC */
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pic_dev = qdev_new(TYPE_HEATHROW);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(pic_dev), &error_fatal);
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/* Connect the heathrow PIC outputs to the 6xx bus */
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for (i = 0; i < smp_cpus; i++) {
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switch (PPC_INPUT(env)) {
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case PPC_FLAGS_INPUT_6xx:
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qdev_connect_gpio_out(pic_dev, 0,
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((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]);
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break;
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default:
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error_report("Bus model not supported on OldWorld Mac machine");
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exit(1);
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}
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}
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/* Timebase Frequency */
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if (kvm_enabled()) {
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tbfreq = kvmppc_get_tbfreq();
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} else {
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tbfreq = TBFREQ;
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}
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/* init basic PC hardware */
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if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
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error_report("Only 6xx bus is supported on heathrow machine");
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exit(1);
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}
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/* Grackle PCI host bridge */
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dev = qdev_new(TYPE_GRACKLE_PCI_HOST_BRIDGE);
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qdev_prop_set_uint32(dev, "ofw-addr", 0x80000000);
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object_property_set_link(OBJECT(dev), "pic", OBJECT(pic_dev),
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&error_abort);
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s = SYS_BUS_DEVICE(dev);
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sysbus_realize_and_unref(s, &error_fatal);
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sysbus_mmio_map(s, 0, GRACKLE_BASE);
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sysbus_mmio_map(s, 1, GRACKLE_BASE + 0x200000);
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/* PCI hole */
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memory_region_add_subregion(get_system_memory(), 0x80000000ULL,
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sysbus_mmio_get_region(s, 2));
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/* Register 2 MB of ISA IO space */
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memory_region_add_subregion(get_system_memory(), 0xfe000000,
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sysbus_mmio_get_region(s, 3));
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pci_bus = PCI_HOST_BRIDGE(dev)->bus;
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pci_vga_init(pci_bus);
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for (i = 0; i < nb_nics; i++) {
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pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
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}
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ide_drive_get(hd, ARRAY_SIZE(hd));
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/* MacIO */
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macio = pci_new(-1, TYPE_OLDWORLD_MACIO);
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dev = DEVICE(macio);
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qdev_prop_set_uint64(dev, "frequency", tbfreq);
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object_property_set_link(OBJECT(macio), "pic", OBJECT(pic_dev),
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&error_abort);
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pci_realize_and_unref(macio, pci_bus, &error_fatal);
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macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
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"ide[0]"));
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macio_ide_init_drives(macio_ide, hd);
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macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
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"ide[1]"));
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macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]);
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dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda"));
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adb_bus = qdev_get_child_bus(dev, "adb.0");
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dev = qdev_new(TYPE_ADB_KEYBOARD);
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qdev_realize_and_unref(dev, adb_bus, &error_fatal);
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dev = qdev_new(TYPE_ADB_MOUSE);
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qdev_realize_and_unref(dev, adb_bus, &error_fatal);
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if (machine_usb(machine)) {
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pci_create_simple(pci_bus, -1, "pci-ohci");
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}
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if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
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graphic_depth = 15;
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/* No PCI init: the BIOS will do it */
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dev = qdev_new(TYPE_FW_CFG_MEM);
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fw_cfg = FW_CFG(dev);
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qdev_prop_set_uint32(dev, "data_width", 1);
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qdev_prop_set_bit(dev, "dma_enabled", false);
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object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
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OBJECT(fw_cfg));
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s = SYS_BUS_DEVICE(dev);
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sysbus_realize_and_unref(s, &error_fatal);
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sysbus_mmio_map(s, 0, CFG_ADDR);
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sysbus_mmio_map(s, 1, CFG_ADDR + 2);
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fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
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fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus);
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fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
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fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW);
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fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
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fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
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if (kernel_cmdline) {
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fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base);
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pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline);
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} else {
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fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
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}
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fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
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fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
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|
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
|
||
|
|
|
||
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
|
||
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
|
||
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
|
||
|
|
|
||
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
|
||
|
|
if (kvm_enabled()) {
|
||
|
|
uint8_t *hypercall;
|
||
|
|
|
||
|
|
hypercall = g_malloc(16);
|
||
|
|
kvmppc_get_hypercall(env, hypercall, 16);
|
||
|
|
fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
|
||
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
|
||
|
|
}
|
||
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq);
|
||
|
|
/* Mac OS X requires a "known good" clock-frequency value; pass it one. */
|
||
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ);
|
||
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ);
|
||
|
|
|
||
|
|
/* MacOS NDRV VGA driver */
|
||
|
|
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME);
|
||
|
|
if (filename) {
|
||
|
|
gchar *ndrv_file;
|
||
|
|
gsize ndrv_size;
|
||
|
|
|
||
|
|
if (g_file_get_contents(filename, &ndrv_file, &ndrv_size, NULL)) {
|
||
|
|
fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size);
|
||
|
|
}
|
||
|
|
g_free(filename);
|
||
|
|
}
|
||
|
|
|
||
|
|
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Implementation of an interface to adjust firmware path
|
||
|
|
* for the bootindex property handling.
|
||
|
|
*/
|
||
|
|
static char *heathrow_fw_dev_path(FWPathProvider *p, BusState *bus,
|
||
|
|
DeviceState *dev)
|
||
|
|
{
|
||
|
|
PCIDevice *pci;
|
||
|
|
IDEBus *ide_bus;
|
||
|
|
IDEState *ide_s;
|
||
|
|
MACIOIDEState *macio_ide;
|
||
|
|
|
||
|
|
if (!strcmp(object_get_typename(OBJECT(dev)), "macio-oldworld")) {
|
||
|
|
pci = PCI_DEVICE(dev);
|
||
|
|
return g_strdup_printf("mac-io@%x", PCI_SLOT(pci->devfn));
|
||
|
|
}
|
||
|
|
|
||
|
|
if (!strcmp(object_get_typename(OBJECT(dev)), "macio-ide")) {
|
||
|
|
macio_ide = MACIO_IDE(dev);
|
||
|
|
return g_strdup_printf("ata-3@%x", macio_ide->addr);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (!strcmp(object_get_typename(OBJECT(dev)), "ide-drive")) {
|
||
|
|
ide_bus = IDE_BUS(qdev_get_parent_bus(dev));
|
||
|
|
ide_s = idebus_active_if(ide_bus);
|
||
|
|
|
||
|
|
if (ide_s->drive_kind == IDE_CD) {
|
||
|
|
return g_strdup("cdrom");
|
||
|
|
}
|
||
|
|
|
||
|
|
return g_strdup("disk");
|
||
|
|
}
|
||
|
|
|
||
|
|
if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) {
|
||
|
|
return g_strdup("disk");
|
||
|
|
}
|
||
|
|
|
||
|
|
if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) {
|
||
|
|
return g_strdup("cdrom");
|
||
|
|
}
|
||
|
|
|
||
|
|
if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) {
|
||
|
|
return g_strdup("disk");
|
||
|
|
}
|
||
|
|
|
||
|
|
return NULL;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int heathrow_kvm_type(MachineState *machine, const char *arg)
|
||
|
|
{
|
||
|
|
/* Always force PR KVM */
|
||
|
|
return 2;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void heathrow_class_init(ObjectClass *oc, void *data)
|
||
|
|
{
|
||
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
||
|
|
FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
|
||
|
|
|
||
|
|
mc->desc = "Heathrow based PowerMAC";
|
||
|
|
mc->init = ppc_heathrow_init;
|
||
|
|
mc->block_default_type = IF_IDE;
|
||
|
|
mc->max_cpus = MAX_CPUS;
|
||
|
|
#ifndef TARGET_PPC64
|
||
|
|
mc->is_default = true;
|
||
|
|
#endif
|
||
|
|
/* TOFIX "cad" when Mac floppy is implemented */
|
||
|
|
mc->default_boot_order = "cd";
|
||
|
|
mc->kvm_type = heathrow_kvm_type;
|
||
|
|
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("750_v3.1");
|
||
|
|
mc->default_display = "std";
|
||
|
|
mc->ignore_boot_device_suffixes = true;
|
||
|
|
mc->default_ram_id = "ppc_heathrow.ram";
|
||
|
|
fwc->get_dev_path = heathrow_fw_dev_path;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const TypeInfo ppc_heathrow_machine_info = {
|
||
|
|
.name = MACHINE_TYPE_NAME("g3beige"),
|
||
|
|
.parent = TYPE_MACHINE,
|
||
|
|
.class_init = heathrow_class_init,
|
||
|
|
.interfaces = (InterfaceInfo[]) {
|
||
|
|
{ TYPE_FW_PATH_PROVIDER },
|
||
|
|
{ }
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static void ppc_heathrow_register_types(void)
|
||
|
|
{
|
||
|
|
type_register_static(&ppc_heathrow_machine_info);
|
||
|
|
}
|
||
|
|
|
||
|
|
type_init(ppc_heathrow_register_types);
|