383 lines
12 KiB
C
383 lines
12 KiB
C
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/*
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* QEMU PowerPC PowerNV Emulation of a few HOMER related registers
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*
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* Copyright (c) 2019, IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qapi/error.h"
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#include "exec/hwaddr.h"
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#include "exec/memory.h"
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#include "sysemu/cpus.h"
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#include "hw/qdev-core.h"
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#include "hw/qdev-properties.h"
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#include "hw/ppc/pnv.h"
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#include "hw/ppc/pnv_homer.h"
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#include "hw/ppc/pnv_xscom.h"
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static bool core_max_array(PnvHomer *homer, hwaddr addr)
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{
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int i;
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PnvHomerClass *hmrc = PNV_HOMER_GET_CLASS(homer);
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for (i = 0; i <= homer->chip->nr_cores; i++) {
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if (addr == (hmrc->core_max_base + i)) {
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return true;
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}
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}
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return false;
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}
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/* P8 Pstate table */
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#define PNV8_OCC_PSTATE_VERSION 0x1f8001
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#define PNV8_OCC_PSTATE_MIN 0x1f8003
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#define PNV8_OCC_PSTATE_VALID 0x1f8000
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#define PNV8_OCC_PSTATE_THROTTLE 0x1f8002
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#define PNV8_OCC_PSTATE_NOM 0x1f8004
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#define PNV8_OCC_PSTATE_TURBO 0x1f8005
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#define PNV8_OCC_PSTATE_ULTRA_TURBO 0x1f8006
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#define PNV8_OCC_PSTATE_DATA 0x1f8008
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#define PNV8_OCC_PSTATE_ID_ZERO 0x1f8010
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#define PNV8_OCC_PSTATE_ID_ONE 0x1f8018
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#define PNV8_OCC_PSTATE_ID_TWO 0x1f8020
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#define PNV8_OCC_VDD_VOLTAGE_IDENTIFIER 0x1f8012
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#define PNV8_OCC_VCS_VOLTAGE_IDENTIFIER 0x1f8013
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#define PNV8_OCC_PSTATE_ZERO_FREQUENCY 0x1f8014
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#define PNV8_OCC_PSTATE_ONE_FREQUENCY 0x1f801c
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#define PNV8_OCC_PSTATE_TWO_FREQUENCY 0x1f8024
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#define PNV8_CORE_MAX_BASE 0x1f8810
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static uint64_t pnv_power8_homer_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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PnvHomer *homer = PNV_HOMER(opaque);
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switch (addr) {
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case PNV8_OCC_PSTATE_VERSION:
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case PNV8_OCC_PSTATE_MIN:
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case PNV8_OCC_PSTATE_ID_ZERO:
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return 0;
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case PNV8_OCC_PSTATE_VALID:
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case PNV8_OCC_PSTATE_THROTTLE:
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case PNV8_OCC_PSTATE_NOM:
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case PNV8_OCC_PSTATE_TURBO:
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case PNV8_OCC_PSTATE_ID_ONE:
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case PNV8_OCC_VDD_VOLTAGE_IDENTIFIER:
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case PNV8_OCC_VCS_VOLTAGE_IDENTIFIER:
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return 1;
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case PNV8_OCC_PSTATE_ULTRA_TURBO:
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case PNV8_OCC_PSTATE_ID_TWO:
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return 2;
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case PNV8_OCC_PSTATE_DATA:
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return 0x1000000000000000;
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/* P8 frequency for 0, 1, and 2 pstates */
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case PNV8_OCC_PSTATE_ZERO_FREQUENCY:
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case PNV8_OCC_PSTATE_ONE_FREQUENCY:
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case PNV8_OCC_PSTATE_TWO_FREQUENCY:
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return 3000;
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}
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/* pstate table core max array */
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if (core_max_array(homer, addr)) {
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return 1;
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}
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return 0;
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}
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static void pnv_power8_homer_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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/* callback function defined to homer write */
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return;
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}
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static const MemoryRegionOps pnv_power8_homer_ops = {
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.read = pnv_power8_homer_read,
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.write = pnv_power8_homer_write,
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.valid.min_access_size = 1,
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.valid.max_access_size = 8,
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.impl.min_access_size = 1,
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.impl.max_access_size = 8,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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/* P8 PBA BARs */
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#define PBA_BAR0 0x00
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#define PBA_BAR1 0x01
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#define PBA_BAR2 0x02
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#define PBA_BAR3 0x03
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#define PBA_BARMASK0 0x04
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#define PBA_BARMASK1 0x05
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#define PBA_BARMASK2 0x06
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#define PBA_BARMASK3 0x07
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static uint64_t pnv_homer_power8_pba_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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PnvHomer *homer = PNV_HOMER(opaque);
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PnvChip *chip = homer->chip;
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uint32_t reg = addr >> 3;
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uint64_t val = 0;
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switch (reg) {
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case PBA_BAR0:
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val = PNV_HOMER_BASE(chip);
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break;
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case PBA_BARMASK0: /* P8 homer region mask */
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val = (PNV_HOMER_SIZE - 1) & 0x300000;
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break;
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case PBA_BAR3: /* P8 occ common area */
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val = PNV_OCC_COMMON_AREA_BASE;
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break;
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case PBA_BARMASK3: /* P8 occ common area mask */
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val = (PNV_OCC_COMMON_AREA_SIZE - 1) & 0x700000;
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "PBA: read to unimplemented register: Ox%"
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HWADDR_PRIx "\n", addr >> 3);
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}
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return val;
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}
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static void pnv_homer_power8_pba_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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qemu_log_mask(LOG_UNIMP, "PBA: write to unimplemented register: Ox%"
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HWADDR_PRIx "\n", addr >> 3);
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}
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static const MemoryRegionOps pnv_homer_power8_pba_ops = {
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.read = pnv_homer_power8_pba_read,
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.write = pnv_homer_power8_pba_write,
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.valid.min_access_size = 8,
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.valid.max_access_size = 8,
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.impl.min_access_size = 8,
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.impl.max_access_size = 8,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static void pnv_homer_power8_class_init(ObjectClass *klass, void *data)
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{
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PnvHomerClass *homer = PNV_HOMER_CLASS(klass);
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homer->pba_size = PNV_XSCOM_PBA_SIZE;
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homer->pba_ops = &pnv_homer_power8_pba_ops;
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homer->homer_size = PNV_HOMER_SIZE;
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homer->homer_ops = &pnv_power8_homer_ops;
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homer->core_max_base = PNV8_CORE_MAX_BASE;
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}
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static const TypeInfo pnv_homer_power8_type_info = {
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.name = TYPE_PNV8_HOMER,
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.parent = TYPE_PNV_HOMER,
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.instance_size = sizeof(PnvHomer),
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.class_init = pnv_homer_power8_class_init,
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};
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/* P9 Pstate table */
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#define PNV9_OCC_PSTATE_ID_ZERO 0xe2018
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#define PNV9_OCC_PSTATE_ID_ONE 0xe2020
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#define PNV9_OCC_PSTATE_ID_TWO 0xe2028
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#define PNV9_OCC_PSTATE_DATA 0xe2000
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#define PNV9_OCC_PSTATE_DATA_AREA 0xe2008
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#define PNV9_OCC_PSTATE_MIN 0xe2003
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#define PNV9_OCC_PSTATE_NOM 0xe2004
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#define PNV9_OCC_PSTATE_TURBO 0xe2005
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#define PNV9_OCC_PSTATE_ULTRA_TURBO 0xe2818
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#define PNV9_OCC_MAX_PSTATE_ULTRA_TURBO 0xe2006
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#define PNV9_OCC_PSTATE_MAJOR_VERSION 0xe2001
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#define PNV9_OCC_OPAL_RUNTIME_DATA 0xe2b85
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#define PNV9_CHIP_HOMER_IMAGE_POINTER 0x200008
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#define PNV9_CHIP_HOMER_BASE 0x0
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#define PNV9_OCC_PSTATE_ZERO_FREQUENCY 0xe201c
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#define PNV9_OCC_PSTATE_ONE_FREQUENCY 0xe2024
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#define PNV9_OCC_PSTATE_TWO_FREQUENCY 0xe202c
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#define PNV9_OCC_ROLE_MASTER_OR_SLAVE 0xe2002
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#define PNV9_CORE_MAX_BASE 0xe2819
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static uint64_t pnv_power9_homer_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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PnvHomer *homer = PNV_HOMER(opaque);
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switch (addr) {
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case PNV9_OCC_MAX_PSTATE_ULTRA_TURBO:
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case PNV9_OCC_PSTATE_ID_ZERO:
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return 0;
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case PNV9_OCC_PSTATE_DATA:
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case PNV9_OCC_ROLE_MASTER_OR_SLAVE:
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case PNV9_OCC_PSTATE_NOM:
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case PNV9_OCC_PSTATE_TURBO:
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case PNV9_OCC_PSTATE_ID_ONE:
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case PNV9_OCC_PSTATE_ULTRA_TURBO:
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case PNV9_OCC_OPAL_RUNTIME_DATA:
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return 1;
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case PNV9_OCC_PSTATE_MIN:
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case PNV9_OCC_PSTATE_ID_TWO:
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return 2;
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/* 3000 khz frequency for 0, 1, and 2 pstates */
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case PNV9_OCC_PSTATE_ZERO_FREQUENCY:
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case PNV9_OCC_PSTATE_ONE_FREQUENCY:
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case PNV9_OCC_PSTATE_TWO_FREQUENCY:
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return 3000;
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case PNV9_OCC_PSTATE_MAJOR_VERSION:
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return 0x90;
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case PNV9_CHIP_HOMER_BASE:
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case PNV9_OCC_PSTATE_DATA_AREA:
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case PNV9_CHIP_HOMER_IMAGE_POINTER:
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return 0x1000000000000000;
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}
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/* pstate table core max array */
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if (core_max_array(homer, addr)) {
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return 1;
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}
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return 0;
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}
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static void pnv_power9_homer_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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/* callback function defined to homer write */
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return;
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}
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static const MemoryRegionOps pnv_power9_homer_ops = {
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.read = pnv_power9_homer_read,
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.write = pnv_power9_homer_write,
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.valid.min_access_size = 1,
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.valid.max_access_size = 8,
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.impl.min_access_size = 1,
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.impl.max_access_size = 8,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static uint64_t pnv_homer_power9_pba_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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PnvHomer *homer = PNV_HOMER(opaque);
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PnvChip *chip = homer->chip;
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uint32_t reg = addr >> 3;
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uint64_t val = 0;
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switch (reg) {
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case PBA_BAR0:
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val = PNV9_HOMER_BASE(chip);
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break;
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case PBA_BARMASK0: /* P9 homer region mask */
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val = (PNV9_HOMER_SIZE - 1) & 0x300000;
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break;
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case PBA_BAR2: /* P9 occ common area */
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val = PNV9_OCC_COMMON_AREA_BASE;
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break;
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case PBA_BARMASK2: /* P9 occ common area size */
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val = (PNV9_OCC_COMMON_AREA_SIZE - 1) & 0x700000;
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "PBA: read to unimplemented register: Ox%"
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HWADDR_PRIx "\n", addr >> 3);
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}
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return val;
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}
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static void pnv_homer_power9_pba_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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qemu_log_mask(LOG_UNIMP, "PBA: write to unimplemented register: Ox%"
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HWADDR_PRIx "\n", addr >> 3);
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}
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static const MemoryRegionOps pnv_homer_power9_pba_ops = {
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.read = pnv_homer_power9_pba_read,
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.write = pnv_homer_power9_pba_write,
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.valid.min_access_size = 8,
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.valid.max_access_size = 8,
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.impl.min_access_size = 8,
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.impl.max_access_size = 8,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static void pnv_homer_power9_class_init(ObjectClass *klass, void *data)
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{
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PnvHomerClass *homer = PNV_HOMER_CLASS(klass);
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homer->pba_size = PNV9_XSCOM_PBA_SIZE;
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homer->pba_ops = &pnv_homer_power9_pba_ops;
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homer->homer_size = PNV9_HOMER_SIZE;
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homer->homer_ops = &pnv_power9_homer_ops;
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homer->core_max_base = PNV9_CORE_MAX_BASE;
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}
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static const TypeInfo pnv_homer_power9_type_info = {
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.name = TYPE_PNV9_HOMER,
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|
.parent = TYPE_PNV_HOMER,
|
||
|
|
.instance_size = sizeof(PnvHomer),
|
||
|
|
.class_init = pnv_homer_power9_class_init,
|
||
|
|
};
|
||
|
|
|
||
|
|
static void pnv_homer_realize(DeviceState *dev, Error **errp)
|
||
|
|
{
|
||
|
|
PnvHomer *homer = PNV_HOMER(dev);
|
||
|
|
PnvHomerClass *hmrc = PNV_HOMER_GET_CLASS(homer);
|
||
|
|
|
||
|
|
assert(homer->chip);
|
||
|
|
|
||
|
|
pnv_xscom_region_init(&homer->pba_regs, OBJECT(dev), hmrc->pba_ops,
|
||
|
|
homer, "xscom-pba", hmrc->pba_size);
|
||
|
|
|
||
|
|
/* homer region */
|
||
|
|
memory_region_init_io(&homer->regs, OBJECT(dev),
|
||
|
|
hmrc->homer_ops, homer, "homer-main-memory",
|
||
|
|
hmrc->homer_size);
|
||
|
|
}
|
||
|
|
|
||
|
|
static Property pnv_homer_properties[] = {
|
||
|
|
DEFINE_PROP_LINK("chip", PnvHomer, chip, TYPE_PNV_CHIP, PnvChip *),
|
||
|
|
DEFINE_PROP_END_OF_LIST(),
|
||
|
|
};
|
||
|
|
|
||
|
|
static void pnv_homer_class_init(ObjectClass *klass, void *data)
|
||
|
|
{
|
||
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
||
|
|
|
||
|
|
dc->realize = pnv_homer_realize;
|
||
|
|
dc->desc = "PowerNV HOMER Memory";
|
||
|
|
device_class_set_props(dc, pnv_homer_properties);
|
||
|
|
dc->user_creatable = false;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const TypeInfo pnv_homer_type_info = {
|
||
|
|
.name = TYPE_PNV_HOMER,
|
||
|
|
.parent = TYPE_DEVICE,
|
||
|
|
.instance_size = sizeof(PnvHomer),
|
||
|
|
.class_init = pnv_homer_class_init,
|
||
|
|
.class_size = sizeof(PnvHomerClass),
|
||
|
|
.abstract = true,
|
||
|
|
};
|
||
|
|
|
||
|
|
static void pnv_homer_register_types(void)
|
||
|
|
{
|
||
|
|
type_register_static(&pnv_homer_type_info);
|
||
|
|
type_register_static(&pnv_homer_power8_type_info);
|
||
|
|
type_register_static(&pnv_homer_power9_type_info);
|
||
|
|
}
|
||
|
|
|
||
|
|
type_init(pnv_homer_register_types);
|