449 lines
15 KiB
C
449 lines
15 KiB
C
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/*
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* QEMU PPC PREP hardware System Emulator
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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* Copyright (c) 2017 Hervé Poussineau
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "hw/rtc/m48t59.h"
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#include "hw/char/serial.h"
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#include "hw/block/fdc.h"
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#include "net/net.h"
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#include "sysemu/sysemu.h"
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#include "hw/isa/isa.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_host.h"
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#include "hw/ppc/ppc.h"
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#include "hw/boards.h"
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#include "qapi/error.h"
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#include "qemu/error-report.h"
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#include "qemu/log.h"
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#include "hw/irq.h"
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#include "hw/loader.h"
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#include "hw/rtc/mc146818rtc.h"
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#include "hw/isa/pc87312.h"
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#include "hw/qdev-properties.h"
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#include "sysemu/arch_init.h"
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#include "sysemu/kvm.h"
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#include "sysemu/qtest.h"
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#include "sysemu/reset.h"
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#include "exec/address-spaces.h"
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#include "trace.h"
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#include "elf.h"
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#include "qemu/units.h"
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#include "kvm_ppc.h"
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/* SMP is not enabled, for now */
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#define MAX_CPUS 1
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#define MAX_IDE_BUS 2
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#define CFG_ADDR 0xf0000510
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#define KERNEL_LOAD_ADDR 0x01000000
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#define INITRD_LOAD_ADDR 0x01800000
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#define NVRAM_SIZE 0x2000
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static void fw_cfg_boot_set(void *opaque, const char *boot_device,
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Error **errp)
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{
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fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
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}
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static void ppc_prep_reset(void *opaque)
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{
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PowerPCCPU *cpu = opaque;
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cpu_reset(CPU(cpu));
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}
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/*****************************************************************************/
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/* NVRAM helpers */
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static inline uint32_t nvram_read(Nvram *nvram, uint32_t addr)
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{
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NvramClass *k = NVRAM_GET_CLASS(nvram);
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return (k->read)(nvram, addr);
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}
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static inline void nvram_write(Nvram *nvram, uint32_t addr, uint32_t val)
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{
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NvramClass *k = NVRAM_GET_CLASS(nvram);
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(k->write)(nvram, addr, val);
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}
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static void NVRAM_set_byte(Nvram *nvram, uint32_t addr, uint8_t value)
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{
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nvram_write(nvram, addr, value);
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}
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static uint8_t NVRAM_get_byte(Nvram *nvram, uint32_t addr)
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{
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return nvram_read(nvram, addr);
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}
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static void NVRAM_set_word(Nvram *nvram, uint32_t addr, uint16_t value)
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{
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nvram_write(nvram, addr, value >> 8);
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nvram_write(nvram, addr + 1, value & 0xFF);
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}
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static uint16_t NVRAM_get_word(Nvram *nvram, uint32_t addr)
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{
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uint16_t tmp;
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tmp = nvram_read(nvram, addr) << 8;
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tmp |= nvram_read(nvram, addr + 1);
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return tmp;
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}
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static void NVRAM_set_lword(Nvram *nvram, uint32_t addr, uint32_t value)
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{
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nvram_write(nvram, addr, value >> 24);
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nvram_write(nvram, addr + 1, (value >> 16) & 0xFF);
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nvram_write(nvram, addr + 2, (value >> 8) & 0xFF);
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nvram_write(nvram, addr + 3, value & 0xFF);
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}
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static void NVRAM_set_string(Nvram *nvram, uint32_t addr, const char *str,
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uint32_t max)
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{
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int i;
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for (i = 0; i < max && str[i] != '\0'; i++) {
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nvram_write(nvram, addr + i, str[i]);
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}
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nvram_write(nvram, addr + i, str[i]);
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nvram_write(nvram, addr + max - 1, '\0');
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}
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static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
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{
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uint16_t tmp;
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uint16_t pd, pd1, pd2;
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tmp = prev >> 8;
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pd = prev ^ value;
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pd1 = pd & 0x000F;
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pd2 = ((pd >> 4) & 0x000F) ^ pd1;
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tmp ^= (pd1 << 3) | (pd1 << 8);
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tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
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return tmp;
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}
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static uint16_t NVRAM_compute_crc (Nvram *nvram, uint32_t start, uint32_t count)
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{
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uint32_t i;
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uint16_t crc = 0xFFFF;
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int odd;
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odd = count & 1;
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count &= ~1;
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for (i = 0; i != count; i++) {
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crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
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}
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if (odd) {
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crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
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}
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return crc;
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}
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#define CMDLINE_ADDR 0x017ff000
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static int PPC_NVRAM_set_params (Nvram *nvram, uint16_t NVRAM_size,
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const char *arch,
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uint32_t RAM_size, int boot_device,
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uint32_t kernel_image, uint32_t kernel_size,
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const char *cmdline,
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uint32_t initrd_image, uint32_t initrd_size,
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uint32_t NVRAM_image,
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int width, int height, int depth)
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{
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uint16_t crc;
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/* Set parameters for Open Hack'Ware BIOS */
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NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
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NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */
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NVRAM_set_word(nvram, 0x14, NVRAM_size);
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NVRAM_set_string(nvram, 0x20, arch, 16);
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NVRAM_set_lword(nvram, 0x30, RAM_size);
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NVRAM_set_byte(nvram, 0x34, boot_device);
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NVRAM_set_lword(nvram, 0x38, kernel_image);
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NVRAM_set_lword(nvram, 0x3C, kernel_size);
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if (cmdline) {
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/* XXX: put the cmdline in NVRAM too ? */
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pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR,
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cmdline);
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NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
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NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
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} else {
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NVRAM_set_lword(nvram, 0x40, 0);
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NVRAM_set_lword(nvram, 0x44, 0);
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}
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NVRAM_set_lword(nvram, 0x48, initrd_image);
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NVRAM_set_lword(nvram, 0x4C, initrd_size);
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NVRAM_set_lword(nvram, 0x50, NVRAM_image);
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NVRAM_set_word(nvram, 0x54, width);
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NVRAM_set_word(nvram, 0x56, height);
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NVRAM_set_word(nvram, 0x58, depth);
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crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
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NVRAM_set_word(nvram, 0xFC, crc);
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return 0;
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}
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static int prep_set_cmos_checksum(DeviceState *dev, void *opaque)
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{
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uint16_t checksum = *(uint16_t *)opaque;
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ISADevice *rtc;
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if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
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rtc = ISA_DEVICE(dev);
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rtc_set_memory(rtc, 0x2e, checksum & 0xff);
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rtc_set_memory(rtc, 0x3e, checksum & 0xff);
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rtc_set_memory(rtc, 0x2f, checksum >> 8);
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rtc_set_memory(rtc, 0x3f, checksum >> 8);
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object_property_add_alias(qdev_get_machine(), "rtc-time", OBJECT(rtc),
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"date");
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}
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return 0;
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}
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static void ibm_40p_init(MachineState *machine)
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{
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CPUPPCState *env = NULL;
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uint16_t cmos_checksum;
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PowerPCCPU *cpu;
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DeviceState *dev, *i82378_dev;
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SysBusDevice *pcihost, *s;
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Nvram *m48t59 = NULL;
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PCIBus *pci_bus;
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ISADevice *isa_dev;
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ISABus *isa_bus;
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void *fw_cfg;
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int i;
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uint32_t kernel_base = 0, initrd_base = 0;
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long kernel_size = 0, initrd_size = 0;
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char boot_device;
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/* init CPU */
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cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
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env = &cpu->env;
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if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
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error_report("only 6xx bus is supported on this machine");
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exit(1);
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}
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if (env->flags & POWERPC_FLAG_RTC_CLK) {
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/* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
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cpu_ppc_tb_init(env, 7812500UL);
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} else {
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/* Set time-base frequency to 100 Mhz */
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cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
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}
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qemu_register_reset(ppc_prep_reset, cpu);
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/* PCI host */
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dev = qdev_new("raven-pcihost");
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if (!bios_name) {
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bios_name = "openbios-ppc";
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}
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qdev_prop_set_string(dev, "bios-name", bios_name);
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qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE);
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pcihost = SYS_BUS_DEVICE(dev);
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object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev));
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sysbus_realize_and_unref(pcihost, &error_fatal);
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pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0"));
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if (!pci_bus) {
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error_report("could not create PCI host controller");
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exit(1);
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}
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/* PCI -> ISA bridge */
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i82378_dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(11, 0), "i82378"));
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qdev_connect_gpio_out(i82378_dev, 0,
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cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
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sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(i82378_dev, 15));
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isa_bus = ISA_BUS(qdev_get_child_bus(i82378_dev, "isa.0"));
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/* Memory controller */
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isa_dev = isa_new("rs6000-mc");
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dev = DEVICE(isa_dev);
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qdev_prop_set_uint32(dev, "ram-size", machine->ram_size);
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isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
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/* RTC */
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isa_dev = isa_new(TYPE_MC146818_RTC);
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dev = DEVICE(isa_dev);
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qdev_prop_set_int32(dev, "base_year", 1900);
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isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
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/* initialize CMOS checksums */
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cmos_checksum = 0x6aa9;
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qbus_walk_children(BUS(isa_bus), prep_set_cmos_checksum, NULL, NULL, NULL,
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&cmos_checksum);
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/* add some more devices */
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if (defaults_enabled()) {
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m48t59 = NVRAM(isa_create_simple(isa_bus, "isa-m48t59"));
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isa_dev = isa_new("cs4231a");
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dev = DEVICE(isa_dev);
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qdev_prop_set_uint32(dev, "iobase", 0x830);
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qdev_prop_set_uint32(dev, "irq", 10);
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isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
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isa_dev = isa_new("pc87312");
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dev = DEVICE(isa_dev);
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qdev_prop_set_uint32(dev, "config", 12);
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isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
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isa_dev = isa_new("prep-systemio");
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dev = DEVICE(isa_dev);
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qdev_prop_set_uint32(dev, "ibm-planar-id", 0xfc);
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qdev_prop_set_uint32(dev, "equipment", 0xc0);
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isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
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dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(1, 0),
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"lsi53c810"));
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lsi53c8xx_handle_legacy_cmdline(dev);
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qdev_connect_gpio_out(dev, 0, qdev_get_gpio_in(i82378_dev, 13));
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|
|
||
|
|
/* XXX: s3-trio at PCI_DEVFN(2, 0) */
|
||
|
|
pci_vga_init(pci_bus);
|
||
|
|
|
||
|
|
for (i = 0; i < nb_nics; i++) {
|
||
|
|
pci_nic_init_nofail(&nd_table[i], pci_bus, "pcnet",
|
||
|
|
i == 0 ? "3" : NULL);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Prepare firmware configuration for OpenBIOS */
|
||
|
|
dev = qdev_new(TYPE_FW_CFG_MEM);
|
||
|
|
fw_cfg = FW_CFG(dev);
|
||
|
|
qdev_prop_set_uint32(dev, "data_width", 1);
|
||
|
|
qdev_prop_set_bit(dev, "dma_enabled", false);
|
||
|
|
object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
|
||
|
|
OBJECT(fw_cfg));
|
||
|
|
s = SYS_BUS_DEVICE(dev);
|
||
|
|
sysbus_realize_and_unref(s, &error_fatal);
|
||
|
|
sysbus_mmio_map(s, 0, CFG_ADDR);
|
||
|
|
sysbus_mmio_map(s, 1, CFG_ADDR + 2);
|
||
|
|
|
||
|
|
if (machine->kernel_filename) {
|
||
|
|
/* load kernel */
|
||
|
|
kernel_base = KERNEL_LOAD_ADDR;
|
||
|
|
kernel_size = load_image_targphys(machine->kernel_filename,
|
||
|
|
kernel_base,
|
||
|
|
machine->ram_size - kernel_base);
|
||
|
|
if (kernel_size < 0) {
|
||
|
|
error_report("could not load kernel '%s'",
|
||
|
|
machine->kernel_filename);
|
||
|
|
exit(1);
|
||
|
|
}
|
||
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
|
||
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
|
||
|
|
/* load initrd */
|
||
|
|
if (machine->initrd_filename) {
|
||
|
|
initrd_base = INITRD_LOAD_ADDR;
|
||
|
|
initrd_size = load_image_targphys(machine->initrd_filename,
|
||
|
|
initrd_base,
|
||
|
|
machine->ram_size - initrd_base);
|
||
|
|
if (initrd_size < 0) {
|
||
|
|
error_report("could not load initial ram disk '%s'",
|
||
|
|
machine->initrd_filename);
|
||
|
|
exit(1);
|
||
|
|
}
|
||
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
|
||
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
|
||
|
|
}
|
||
|
|
if (machine->kernel_cmdline && *machine->kernel_cmdline) {
|
||
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
|
||
|
|
pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
|
||
|
|
machine->kernel_cmdline);
|
||
|
|
fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA,
|
||
|
|
machine->kernel_cmdline);
|
||
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
|
||
|
|
strlen(machine->kernel_cmdline) + 1);
|
||
|
|
}
|
||
|
|
boot_device = 'm';
|
||
|
|
} else {
|
||
|
|
boot_device = machine->boot_order[0];
|
||
|
|
}
|
||
|
|
|
||
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus);
|
||
|
|
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
|
||
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_PREP);
|
||
|
|
|
||
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
|
||
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
|
||
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
|
||
|
|
|
||
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
|
||
|
|
if (kvm_enabled()) {
|
||
|
|
uint8_t *hypercall;
|
||
|
|
|
||
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq());
|
||
|
|
hypercall = g_malloc(16);
|
||
|
|
kvmppc_get_hypercall(env, hypercall, 16);
|
||
|
|
fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
|
||
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
|
||
|
|
} else {
|
||
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, NANOSECONDS_PER_SECOND);
|
||
|
|
}
|
||
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device);
|
||
|
|
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
|
||
|
|
|
||
|
|
/* Prepare firmware configuration for Open Hack'Ware */
|
||
|
|
if (m48t59) {
|
||
|
|
PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", ram_size,
|
||
|
|
boot_device,
|
||
|
|
kernel_base, kernel_size,
|
||
|
|
machine->kernel_cmdline,
|
||
|
|
initrd_base, initrd_size,
|
||
|
|
/* XXX: need an option to load a NVRAM image */
|
||
|
|
0,
|
||
|
|
graphic_width, graphic_height, graphic_depth);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static void ibm_40p_machine_init(MachineClass *mc)
|
||
|
|
{
|
||
|
|
mc->desc = "IBM RS/6000 7020 (40p)",
|
||
|
|
mc->init = ibm_40p_init;
|
||
|
|
mc->max_cpus = 1;
|
||
|
|
mc->default_ram_size = 128 * MiB;
|
||
|
|
mc->block_default_type = IF_SCSI;
|
||
|
|
mc->default_boot_order = "c";
|
||
|
|
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("604");
|
||
|
|
mc->default_display = "std";
|
||
|
|
}
|
||
|
|
|
||
|
|
DEFINE_MACHINE("40p", ibm_40p_machine_init)
|