246 lines
9.1 KiB
C
246 lines
9.1 KiB
C
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/*
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* QEMU RISC-V Spike Board
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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* Copyright (c) 2017-2018 SiFive, Inc.
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*
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* This provides a RISC-V Board with the following devices:
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*
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* 0) HTIF Console and Poweroff
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* 1) CLINT (Timer and IPI)
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* 2) PLIC (Platform Level Interrupt Controller)
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "hw/boards.h"
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#include "hw/loader.h"
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#include "hw/sysbus.h"
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#include "target/riscv/cpu.h"
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#include "hw/riscv/riscv_htif.h"
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#include "hw/riscv/riscv_hart.h"
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#include "hw/riscv/sifive_clint.h"
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#include "hw/riscv/spike.h"
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#include "hw/riscv/boot.h"
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#include "chardev/char.h"
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#include "sysemu/arch_init.h"
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#include "sysemu/device_tree.h"
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#include "sysemu/qtest.h"
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#include "sysemu/sysemu.h"
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#if defined(TARGET_RISCV32)
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# define BIOS_FILENAME "opensbi-riscv32-spike-fw_jump.elf"
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#else
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# define BIOS_FILENAME "opensbi-riscv64-spike-fw_jump.elf"
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#endif
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static const struct MemmapEntry {
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hwaddr base;
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hwaddr size;
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} spike_memmap[] = {
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[SPIKE_MROM] = { 0x1000, 0xf000 },
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[SPIKE_CLINT] = { 0x2000000, 0x10000 },
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[SPIKE_DRAM] = { 0x80000000, 0x0 },
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};
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static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap,
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uint64_t mem_size, const char *cmdline)
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{
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void *fdt;
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int cpu;
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uint32_t *cells;
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char *nodename;
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fdt = s->fdt = create_device_tree(&s->fdt_size);
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if (!fdt) {
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error_report("create_device_tree() failed");
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exit(1);
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}
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qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu");
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qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev");
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qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
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qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
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qemu_fdt_add_subnode(fdt, "/htif");
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qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0");
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qemu_fdt_add_subnode(fdt, "/soc");
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qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
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qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
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qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
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qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
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nodename = g_strdup_printf("/memory@%lx",
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(long)memmap[SPIKE_DRAM].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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memmap[SPIKE_DRAM].base >> 32, memmap[SPIKE_DRAM].base,
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mem_size >> 32, mem_size);
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qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
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g_free(nodename);
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qemu_fdt_add_subnode(fdt, "/cpus");
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qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
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SIFIVE_CLINT_TIMEBASE_FREQ);
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qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
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qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
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for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
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nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
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char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
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char *isa = riscv_isa_string(&s->soc.harts[cpu]);
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qemu_fdt_add_subnode(fdt, nodename);
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#if defined(TARGET_RISCV32)
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qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32");
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#else
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qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
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#endif
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qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
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qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
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qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
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qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
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qemu_fdt_add_subnode(fdt, intc);
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qemu_fdt_setprop_cell(fdt, intc, "phandle", 1);
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qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
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qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
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qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
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g_free(isa);
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g_free(intc);
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g_free(nodename);
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}
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cells = g_new0(uint32_t, s->soc.num_harts * 4);
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for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
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nodename =
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g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
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uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
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cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
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cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
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cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
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cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
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g_free(nodename);
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}
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nodename = g_strdup_printf("/soc/clint@%lx",
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(long)memmap[SPIKE_CLINT].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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0x0, memmap[SPIKE_CLINT].base,
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0x0, memmap[SPIKE_CLINT].size);
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qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
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cells, s->soc.num_harts * sizeof(uint32_t) * 4);
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g_free(cells);
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g_free(nodename);
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if (cmdline) {
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qemu_fdt_add_subnode(fdt, "/chosen");
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qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
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}
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}
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static void spike_board_init(MachineState *machine)
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{
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const struct MemmapEntry *memmap = spike_memmap;
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SpikeState *s = g_new0(SpikeState, 1);
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MemoryRegion *system_memory = get_system_memory();
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MemoryRegion *main_mem = g_new(MemoryRegion, 1);
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MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
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unsigned int smp_cpus = machine->smp.cpus;
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uint32_t fdt_load_addr;
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uint64_t kernel_entry;
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/* Initialize SOC */
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object_initialize_child(OBJECT(machine), "soc", &s->soc,
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TYPE_RISCV_HART_ARRAY);
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object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type,
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&error_abort);
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object_property_set_int(OBJECT(&s->soc), "num-harts", smp_cpus,
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&error_abort);
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sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_abort);
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/* register system main memory (actual RAM) */
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memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
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machine->ram_size, &error_fatal);
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memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
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main_mem);
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/* create device tree */
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create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
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/* boot rom */
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memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
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memmap[SPIKE_MROM].size, &error_fatal);
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memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
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mask_rom);
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riscv_find_and_load_firmware(machine, BIOS_FILENAME,
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memmap[SPIKE_DRAM].base,
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htif_symbol_callback);
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if (machine->kernel_filename) {
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kernel_entry = riscv_load_kernel(machine->kernel_filename,
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htif_symbol_callback);
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if (machine->initrd_filename) {
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hwaddr start;
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hwaddr end = riscv_load_initrd(machine->initrd_filename,
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machine->ram_size, kernel_entry,
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&start);
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qemu_fdt_setprop_cell(s->fdt, "/chosen",
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"linux,initrd-start", start);
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qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
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end);
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}
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} else {
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/*
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* If dynamic firmware is used, it doesn't know where is the next mode
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* if kernel argument is not set.
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*/
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kernel_entry = 0;
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}
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/* Compute the fdt load address in dram */
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fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base,
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machine->ram_size, s->fdt);
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/* load the reset vector */
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riscv_setup_rom_reset_vec(memmap[SPIKE_DRAM].base, memmap[SPIKE_MROM].base,
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memmap[SPIKE_MROM].size, kernel_entry,
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fdt_load_addr, s->fdt);
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/* initialize HTIF using symbols found in load_kernel */
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htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0));
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/* Core Local Interruptor (timer and IPI) */
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sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
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smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
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false);
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}
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static void spike_machine_init(MachineClass *mc)
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{
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mc->desc = "RISC-V Spike Board";
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mc->init = spike_board_init;
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mc->max_cpus = 8;
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mc->is_default = true;
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mc->default_cpu_type = SPIKE_V1_10_0_CPU;
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}
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DEFINE_MACHINE("spike", spike_machine_init)
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