640 lines
25 KiB
C
640 lines
25 KiB
C
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/*
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* QEMU RISC-V VirtIO Board
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*
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* Copyright (c) 2017 SiFive, Inc.
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*
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* RISC-V machine with 16550a UART and VirtIO MMIO
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qemu/log.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "hw/boards.h"
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#include "hw/loader.h"
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#include "hw/sysbus.h"
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#include "hw/qdev-properties.h"
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#include "hw/char/serial.h"
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#include "target/riscv/cpu.h"
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#include "hw/riscv/riscv_hart.h"
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#include "hw/riscv/sifive_plic.h"
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#include "hw/riscv/sifive_clint.h"
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#include "hw/riscv/sifive_test.h"
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#include "hw/riscv/virt.h"
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#include "hw/riscv/boot.h"
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#include "chardev/char.h"
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#include "sysemu/arch_init.h"
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#include "sysemu/device_tree.h"
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#include "sysemu/sysemu.h"
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#include "hw/pci/pci.h"
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#include "hw/pci-host/gpex.h"
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#if defined(TARGET_RISCV32)
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# define BIOS_FILENAME "opensbi-riscv32-virt-fw_jump.bin"
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#else
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# define BIOS_FILENAME "opensbi-riscv64-virt-fw_jump.bin"
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#endif
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static const struct MemmapEntry {
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hwaddr base;
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hwaddr size;
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} virt_memmap[] = {
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[VIRT_DEBUG] = { 0x0, 0x100 },
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[VIRT_MROM] = { 0x1000, 0xf000 },
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[VIRT_TEST] = { 0x100000, 0x1000 },
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[VIRT_RTC] = { 0x101000, 0x1000 },
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[VIRT_CLINT] = { 0x2000000, 0x10000 },
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[VIRT_PCIE_PIO] = { 0x3000000, 0x10000 },
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[VIRT_PLIC] = { 0xc000000, 0x4000000 },
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[VIRT_UART0] = { 0x10000000, 0x100 },
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[VIRT_VIRTIO] = { 0x10001000, 0x1000 },
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[VIRT_FLASH] = { 0x20000000, 0x4000000 },
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[VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 },
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[VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
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[VIRT_DRAM] = { 0x80000000, 0x0 },
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};
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#define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
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static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s,
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const char *name,
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const char *alias_prop_name)
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{
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/*
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* Create a single flash device. We use the same parameters as
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* the flash devices on the ARM virt board.
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*/
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DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
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qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
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qdev_prop_set_uint8(dev, "width", 4);
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qdev_prop_set_uint8(dev, "device-width", 2);
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qdev_prop_set_bit(dev, "big-endian", false);
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qdev_prop_set_uint16(dev, "id0", 0x89);
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qdev_prop_set_uint16(dev, "id1", 0x18);
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qdev_prop_set_uint16(dev, "id2", 0x00);
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qdev_prop_set_uint16(dev, "id3", 0x00);
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qdev_prop_set_string(dev, "name", name);
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object_property_add_child(OBJECT(s), name, OBJECT(dev));
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object_property_add_alias(OBJECT(s), alias_prop_name,
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OBJECT(dev), "drive");
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return PFLASH_CFI01(dev);
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}
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static void virt_flash_create(RISCVVirtState *s)
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{
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s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0");
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s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1");
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}
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static void virt_flash_map1(PFlashCFI01 *flash,
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hwaddr base, hwaddr size,
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MemoryRegion *sysmem)
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{
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DeviceState *dev = DEVICE(flash);
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assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE));
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assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
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qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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memory_region_add_subregion(sysmem, base,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
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0));
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}
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static void virt_flash_map(RISCVVirtState *s,
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MemoryRegion *sysmem)
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{
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hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
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hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
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virt_flash_map1(s->flash[0], flashbase, flashsize,
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sysmem);
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virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize,
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sysmem);
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}
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static void create_pcie_irq_map(void *fdt, char *nodename,
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uint32_t plic_phandle)
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{
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int pin, dev;
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uint32_t
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full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * FDT_INT_MAP_WIDTH] = {};
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uint32_t *irq_map = full_irq_map;
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/* This code creates a standard swizzle of interrupts such that
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* each device's first interrupt is based on it's PCI_SLOT number.
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* (See pci_swizzle_map_irq_fn())
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*
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* We only need one entry per interrupt in the table (not one per
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* possible slot) seeing the interrupt-map-mask will allow the table
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* to wrap to any number of devices.
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*/
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for (dev = 0; dev < GPEX_NUM_IRQS; dev++) {
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int devfn = dev * 0x8;
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for (pin = 0; pin < GPEX_NUM_IRQS; pin++) {
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int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS);
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int i = 0;
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irq_map[i] = cpu_to_be32(devfn << 8);
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i += FDT_PCI_ADDR_CELLS;
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irq_map[i] = cpu_to_be32(pin + 1);
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i += FDT_PCI_INT_CELLS;
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irq_map[i++] = cpu_to_be32(plic_phandle);
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i += FDT_PLIC_ADDR_CELLS;
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irq_map[i] = cpu_to_be32(irq_nr);
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irq_map += FDT_INT_MAP_WIDTH;
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}
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}
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qemu_fdt_setprop(fdt, nodename, "interrupt-map",
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full_irq_map, sizeof(full_irq_map));
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qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask",
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0x1800, 0, 0, 0x7);
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}
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static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
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uint64_t mem_size, const char *cmdline)
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{
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void *fdt;
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int cpu, i;
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uint32_t *cells;
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char *nodename;
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uint32_t plic_phandle, test_phandle, phandle = 1;
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hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
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hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
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fdt = s->fdt = create_device_tree(&s->fdt_size);
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if (!fdt) {
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error_report("create_device_tree() failed");
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exit(1);
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}
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qemu_fdt_setprop_string(fdt, "/", "model", "riscv-virtio,qemu");
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qemu_fdt_setprop_string(fdt, "/", "compatible", "riscv-virtio");
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qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
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qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
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qemu_fdt_add_subnode(fdt, "/soc");
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qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
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qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
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qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
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qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
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nodename = g_strdup_printf("/memory@%lx",
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(long)memmap[VIRT_DRAM].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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memmap[VIRT_DRAM].base >> 32, memmap[VIRT_DRAM].base,
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mem_size >> 32, mem_size);
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qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
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g_free(nodename);
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qemu_fdt_add_subnode(fdt, "/cpus");
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qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
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SIFIVE_CLINT_TIMEBASE_FREQ);
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qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
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qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
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for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
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int cpu_phandle = phandle++;
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int intc_phandle;
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nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
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char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
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char *isa = riscv_isa_string(&s->soc.harts[cpu]);
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qemu_fdt_add_subnode(fdt, nodename);
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#if defined(TARGET_RISCV32)
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qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32");
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#else
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qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
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#endif
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qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
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qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
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qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
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qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
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qemu_fdt_setprop_cell(fdt, nodename, "phandle", cpu_phandle);
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intc_phandle = phandle++;
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qemu_fdt_add_subnode(fdt, intc);
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qemu_fdt_setprop_cell(fdt, intc, "phandle", intc_phandle);
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qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
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qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
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qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
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g_free(isa);
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g_free(intc);
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g_free(nodename);
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}
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/* Add cpu-topology node */
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qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
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qemu_fdt_add_subnode(fdt, "/cpus/cpu-map/cluster0");
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for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
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char *core_nodename = g_strdup_printf("/cpus/cpu-map/cluster0/core%d",
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cpu);
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char *cpu_nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
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uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, cpu_nodename);
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qemu_fdt_add_subnode(fdt, core_nodename);
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qemu_fdt_setprop_cell(fdt, core_nodename, "cpu", intc_phandle);
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g_free(core_nodename);
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g_free(cpu_nodename);
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}
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cells = g_new0(uint32_t, s->soc.num_harts * 4);
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for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
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nodename =
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g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
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uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
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cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
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cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
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cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
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cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
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g_free(nodename);
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}
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nodename = g_strdup_printf("/soc/clint@%lx",
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(long)memmap[VIRT_CLINT].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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0x0, memmap[VIRT_CLINT].base,
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0x0, memmap[VIRT_CLINT].size);
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qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
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cells, s->soc.num_harts * sizeof(uint32_t) * 4);
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g_free(cells);
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g_free(nodename);
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plic_phandle = phandle++;
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cells = g_new0(uint32_t, s->soc.num_harts * 4);
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for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
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nodename =
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g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
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uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
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cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
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cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
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cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
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cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
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g_free(nodename);
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}
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nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
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(long)memmap[VIRT_PLIC].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cell(fdt, nodename, "#address-cells",
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FDT_PLIC_ADDR_CELLS);
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|
|
qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells",
|
||
|
|
FDT_PLIC_INT_CELLS);
|
||
|
|
qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
|
||
|
|
qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
|
||
|
|
qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
|
||
|
|
cells, s->soc.num_harts * sizeof(uint32_t) * 4);
|
||
|
|
qemu_fdt_setprop_cells(fdt, nodename, "reg",
|
||
|
|
0x0, memmap[VIRT_PLIC].base,
|
||
|
|
0x0, memmap[VIRT_PLIC].size);
|
||
|
|
qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV);
|
||
|
|
qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
|
||
|
|
plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
|
||
|
|
g_free(cells);
|
||
|
|
g_free(nodename);
|
||
|
|
|
||
|
|
for (i = 0; i < VIRTIO_COUNT; i++) {
|
||
|
|
nodename = g_strdup_printf("/virtio_mmio@%lx",
|
||
|
|
(long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size));
|
||
|
|
qemu_fdt_add_subnode(fdt, nodename);
|
||
|
|
qemu_fdt_setprop_string(fdt, nodename, "compatible", "virtio,mmio");
|
||
|
|
qemu_fdt_setprop_cells(fdt, nodename, "reg",
|
||
|
|
0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
|
||
|
|
0x0, memmap[VIRT_VIRTIO].size);
|
||
|
|
qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
|
||
|
|
qemu_fdt_setprop_cell(fdt, nodename, "interrupts", VIRTIO_IRQ + i);
|
||
|
|
g_free(nodename);
|
||
|
|
}
|
||
|
|
|
||
|
|
nodename = g_strdup_printf("/soc/pci@%lx",
|
||
|
|
(long) memmap[VIRT_PCIE_ECAM].base);
|
||
|
|
qemu_fdt_add_subnode(fdt, nodename);
|
||
|
|
qemu_fdt_setprop_cell(fdt, nodename, "#address-cells",
|
||
|
|
FDT_PCI_ADDR_CELLS);
|
||
|
|
qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells",
|
||
|
|
FDT_PCI_INT_CELLS);
|
||
|
|
qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0x2);
|
||
|
|
qemu_fdt_setprop_string(fdt, nodename, "compatible",
|
||
|
|
"pci-host-ecam-generic");
|
||
|
|
qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci");
|
||
|
|
qemu_fdt_setprop_cell(fdt, nodename, "linux,pci-domain", 0);
|
||
|
|
qemu_fdt_setprop_cells(fdt, nodename, "bus-range", 0,
|
||
|
|
memmap[VIRT_PCIE_ECAM].size /
|
||
|
|
PCIE_MMCFG_SIZE_MIN - 1);
|
||
|
|
qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);
|
||
|
|
qemu_fdt_setprop_cells(fdt, nodename, "reg", 0, memmap[VIRT_PCIE_ECAM].base,
|
||
|
|
0, memmap[VIRT_PCIE_ECAM].size);
|
||
|
|
qemu_fdt_setprop_sized_cells(fdt, nodename, "ranges",
|
||
|
|
1, FDT_PCI_RANGE_IOPORT, 2, 0,
|
||
|
|
2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size,
|
||
|
|
1, FDT_PCI_RANGE_MMIO,
|
||
|
|
2, memmap[VIRT_PCIE_MMIO].base,
|
||
|
|
2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size);
|
||
|
|
create_pcie_irq_map(fdt, nodename, plic_phandle);
|
||
|
|
g_free(nodename);
|
||
|
|
|
||
|
|
test_phandle = phandle++;
|
||
|
|
nodename = g_strdup_printf("/test@%lx",
|
||
|
|
(long)memmap[VIRT_TEST].base);
|
||
|
|
qemu_fdt_add_subnode(fdt, nodename);
|
||
|
|
{
|
||
|
|
const char compat[] = "sifive,test1\0sifive,test0\0syscon";
|
||
|
|
qemu_fdt_setprop(fdt, nodename, "compatible", compat, sizeof(compat));
|
||
|
|
}
|
||
|
|
qemu_fdt_setprop_cells(fdt, nodename, "reg",
|
||
|
|
0x0, memmap[VIRT_TEST].base,
|
||
|
|
0x0, memmap[VIRT_TEST].size);
|
||
|
|
qemu_fdt_setprop_cell(fdt, nodename, "phandle", test_phandle);
|
||
|
|
test_phandle = qemu_fdt_get_phandle(fdt, nodename);
|
||
|
|
g_free(nodename);
|
||
|
|
|
||
|
|
nodename = g_strdup_printf("/reboot");
|
||
|
|
qemu_fdt_add_subnode(fdt, nodename);
|
||
|
|
qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon-reboot");
|
||
|
|
qemu_fdt_setprop_cell(fdt, nodename, "regmap", test_phandle);
|
||
|
|
qemu_fdt_setprop_cell(fdt, nodename, "offset", 0x0);
|
||
|
|
qemu_fdt_setprop_cell(fdt, nodename, "value", FINISHER_RESET);
|
||
|
|
g_free(nodename);
|
||
|
|
|
||
|
|
nodename = g_strdup_printf("/poweroff");
|
||
|
|
qemu_fdt_add_subnode(fdt, nodename);
|
||
|
|
qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon-poweroff");
|
||
|
|
qemu_fdt_setprop_cell(fdt, nodename, "regmap", test_phandle);
|
||
|
|
qemu_fdt_setprop_cell(fdt, nodename, "offset", 0x0);
|
||
|
|
qemu_fdt_setprop_cell(fdt, nodename, "value", FINISHER_PASS);
|
||
|
|
g_free(nodename);
|
||
|
|
|
||
|
|
nodename = g_strdup_printf("/uart@%lx",
|
||
|
|
(long)memmap[VIRT_UART0].base);
|
||
|
|
qemu_fdt_add_subnode(fdt, nodename);
|
||
|
|
qemu_fdt_setprop_string(fdt, nodename, "compatible", "ns16550a");
|
||
|
|
qemu_fdt_setprop_cells(fdt, nodename, "reg",
|
||
|
|
0x0, memmap[VIRT_UART0].base,
|
||
|
|
0x0, memmap[VIRT_UART0].size);
|
||
|
|
qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400);
|
||
|
|
qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
|
||
|
|
qemu_fdt_setprop_cell(fdt, nodename, "interrupts", UART0_IRQ);
|
||
|
|
|
||
|
|
qemu_fdt_add_subnode(fdt, "/chosen");
|
||
|
|
qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
|
||
|
|
if (cmdline) {
|
||
|
|
qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
|
||
|
|
}
|
||
|
|
g_free(nodename);
|
||
|
|
|
||
|
|
nodename = g_strdup_printf("/rtc@%lx",
|
||
|
|
(long)memmap[VIRT_RTC].base);
|
||
|
|
qemu_fdt_add_subnode(fdt, nodename);
|
||
|
|
qemu_fdt_setprop_string(fdt, nodename, "compatible",
|
||
|
|
"google,goldfish-rtc");
|
||
|
|
qemu_fdt_setprop_cells(fdt, nodename, "reg",
|
||
|
|
0x0, memmap[VIRT_RTC].base,
|
||
|
|
0x0, memmap[VIRT_RTC].size);
|
||
|
|
qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
|
||
|
|
qemu_fdt_setprop_cell(fdt, nodename, "interrupts", RTC_IRQ);
|
||
|
|
g_free(nodename);
|
||
|
|
|
||
|
|
nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
|
||
|
|
qemu_fdt_add_subnode(s->fdt, nodename);
|
||
|
|
qemu_fdt_setprop_string(s->fdt, nodename, "compatible", "cfi-flash");
|
||
|
|
qemu_fdt_setprop_sized_cells(s->fdt, nodename, "reg",
|
||
|
|
2, flashbase, 2, flashsize,
|
||
|
|
2, flashbase + flashsize, 2, flashsize);
|
||
|
|
qemu_fdt_setprop_cell(s->fdt, nodename, "bank-width", 4);
|
||
|
|
g_free(nodename);
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
|
||
|
|
hwaddr ecam_base, hwaddr ecam_size,
|
||
|
|
hwaddr mmio_base, hwaddr mmio_size,
|
||
|
|
hwaddr pio_base,
|
||
|
|
DeviceState *plic, bool link_up)
|
||
|
|
{
|
||
|
|
DeviceState *dev;
|
||
|
|
MemoryRegion *ecam_alias, *ecam_reg;
|
||
|
|
MemoryRegion *mmio_alias, *mmio_reg;
|
||
|
|
qemu_irq irq;
|
||
|
|
int i;
|
||
|
|
|
||
|
|
dev = qdev_new(TYPE_GPEX_HOST);
|
||
|
|
|
||
|
|
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
|
||
|
|
|
||
|
|
ecam_alias = g_new0(MemoryRegion, 1);
|
||
|
|
ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
|
||
|
|
memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
|
||
|
|
ecam_reg, 0, ecam_size);
|
||
|
|
memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias);
|
||
|
|
|
||
|
|
mmio_alias = g_new0(MemoryRegion, 1);
|
||
|
|
mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
|
||
|
|
memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
|
||
|
|
mmio_reg, mmio_base, mmio_size);
|
||
|
|
memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias);
|
||
|
|
|
||
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base);
|
||
|
|
|
||
|
|
for (i = 0; i < GPEX_NUM_IRQS; i++) {
|
||
|
|
irq = qdev_get_gpio_in(plic, PCIE_IRQ + i);
|
||
|
|
|
||
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);
|
||
|
|
gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i);
|
||
|
|
}
|
||
|
|
|
||
|
|
return dev;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void virt_machine_init(MachineState *machine)
|
||
|
|
{
|
||
|
|
const struct MemmapEntry *memmap = virt_memmap;
|
||
|
|
RISCVVirtState *s = RISCV_VIRT_MACHINE(machine);
|
||
|
|
MemoryRegion *system_memory = get_system_memory();
|
||
|
|
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
|
||
|
|
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
|
||
|
|
char *plic_hart_config;
|
||
|
|
size_t plic_hart_config_len;
|
||
|
|
target_ulong start_addr = memmap[VIRT_DRAM].base;
|
||
|
|
uint32_t fdt_load_addr;
|
||
|
|
uint64_t kernel_entry;
|
||
|
|
int i;
|
||
|
|
unsigned int smp_cpus = machine->smp.cpus;
|
||
|
|
|
||
|
|
/* Initialize SOC */
|
||
|
|
object_initialize_child(OBJECT(machine), "soc", &s->soc,
|
||
|
|
TYPE_RISCV_HART_ARRAY);
|
||
|
|
object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type,
|
||
|
|
&error_abort);
|
||
|
|
object_property_set_int(OBJECT(&s->soc), "num-harts", smp_cpus,
|
||
|
|
&error_abort);
|
||
|
|
sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_abort);
|
||
|
|
|
||
|
|
/* register system main memory (actual RAM) */
|
||
|
|
memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram",
|
||
|
|
machine->ram_size, &error_fatal);
|
||
|
|
memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base,
|
||
|
|
main_mem);
|
||
|
|
|
||
|
|
/* create device tree */
|
||
|
|
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
|
||
|
|
|
||
|
|
/* boot rom */
|
||
|
|
memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
|
||
|
|
memmap[VIRT_MROM].size, &error_fatal);
|
||
|
|
memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
|
||
|
|
mask_rom);
|
||
|
|
|
||
|
|
riscv_find_and_load_firmware(machine, BIOS_FILENAME,
|
||
|
|
memmap[VIRT_DRAM].base, NULL);
|
||
|
|
|
||
|
|
if (machine->kernel_filename) {
|
||
|
|
kernel_entry = riscv_load_kernel(machine->kernel_filename, NULL);
|
||
|
|
|
||
|
|
if (machine->initrd_filename) {
|
||
|
|
hwaddr start;
|
||
|
|
hwaddr end = riscv_load_initrd(machine->initrd_filename,
|
||
|
|
machine->ram_size, kernel_entry,
|
||
|
|
&start);
|
||
|
|
qemu_fdt_setprop_cell(s->fdt, "/chosen",
|
||
|
|
"linux,initrd-start", start);
|
||
|
|
qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
|
||
|
|
end);
|
||
|
|
}
|
||
|
|
} else {
|
||
|
|
/*
|
||
|
|
* If dynamic firmware is used, it doesn't know where is the next mode
|
||
|
|
* if kernel argument is not set.
|
||
|
|
*/
|
||
|
|
kernel_entry = 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (drive_get(IF_PFLASH, 0, 0)) {
|
||
|
|
/*
|
||
|
|
* Pflash was supplied, let's overwrite the address we jump to after
|
||
|
|
* reset to the base of the flash.
|
||
|
|
*/
|
||
|
|
start_addr = virt_memmap[VIRT_FLASH].base;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Compute the fdt load address in dram */
|
||
|
|
fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
|
||
|
|
machine->ram_size, s->fdt);
|
||
|
|
/* load the reset vector */
|
||
|
|
riscv_setup_rom_reset_vec(start_addr, virt_memmap[VIRT_MROM].base,
|
||
|
|
virt_memmap[VIRT_MROM].size, kernel_entry,
|
||
|
|
fdt_load_addr, s->fdt);
|
||
|
|
|
||
|
|
/* create PLIC hart topology configuration string */
|
||
|
|
plic_hart_config_len = (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpus;
|
||
|
|
plic_hart_config = g_malloc0(plic_hart_config_len);
|
||
|
|
for (i = 0; i < smp_cpus; i++) {
|
||
|
|
if (i != 0) {
|
||
|
|
strncat(plic_hart_config, ",", plic_hart_config_len);
|
||
|
|
}
|
||
|
|
strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG, plic_hart_config_len);
|
||
|
|
plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* MMIO */
|
||
|
|
s->plic = sifive_plic_create(memmap[VIRT_PLIC].base,
|
||
|
|
plic_hart_config,
|
||
|
|
VIRT_PLIC_NUM_SOURCES,
|
||
|
|
VIRT_PLIC_NUM_PRIORITIES,
|
||
|
|
VIRT_PLIC_PRIORITY_BASE,
|
||
|
|
VIRT_PLIC_PENDING_BASE,
|
||
|
|
VIRT_PLIC_ENABLE_BASE,
|
||
|
|
VIRT_PLIC_ENABLE_STRIDE,
|
||
|
|
VIRT_PLIC_CONTEXT_BASE,
|
||
|
|
VIRT_PLIC_CONTEXT_STRIDE,
|
||
|
|
memmap[VIRT_PLIC].size);
|
||
|
|
sifive_clint_create(memmap[VIRT_CLINT].base,
|
||
|
|
memmap[VIRT_CLINT].size, smp_cpus,
|
||
|
|
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, true);
|
||
|
|
sifive_test_create(memmap[VIRT_TEST].base);
|
||
|
|
|
||
|
|
for (i = 0; i < VIRTIO_COUNT; i++) {
|
||
|
|
sysbus_create_simple("virtio-mmio",
|
||
|
|
memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
|
||
|
|
qdev_get_gpio_in(DEVICE(s->plic), VIRTIO_IRQ + i));
|
||
|
|
}
|
||
|
|
|
||
|
|
gpex_pcie_init(system_memory,
|
||
|
|
memmap[VIRT_PCIE_ECAM].base,
|
||
|
|
memmap[VIRT_PCIE_ECAM].size,
|
||
|
|
memmap[VIRT_PCIE_MMIO].base,
|
||
|
|
memmap[VIRT_PCIE_MMIO].size,
|
||
|
|
memmap[VIRT_PCIE_PIO].base,
|
||
|
|
DEVICE(s->plic), true);
|
||
|
|
|
||
|
|
serial_mm_init(system_memory, memmap[VIRT_UART0].base,
|
||
|
|
0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193,
|
||
|
|
serial_hd(0), DEVICE_LITTLE_ENDIAN);
|
||
|
|
|
||
|
|
sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base,
|
||
|
|
qdev_get_gpio_in(DEVICE(s->plic), RTC_IRQ));
|
||
|
|
|
||
|
|
virt_flash_create(s);
|
||
|
|
|
||
|
|
for (i = 0; i < ARRAY_SIZE(s->flash); i++) {
|
||
|
|
/* Map legacy -drive if=pflash to machine properties */
|
||
|
|
pflash_cfi01_legacy_drive(s->flash[i],
|
||
|
|
drive_get(IF_PFLASH, 0, i));
|
||
|
|
}
|
||
|
|
virt_flash_map(s, system_memory);
|
||
|
|
|
||
|
|
g_free(plic_hart_config);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void virt_machine_instance_init(Object *obj)
|
||
|
|
{
|
||
|
|
}
|
||
|
|
|
||
|
|
static void virt_machine_class_init(ObjectClass *oc, void *data)
|
||
|
|
{
|
||
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
||
|
|
|
||
|
|
mc->desc = "RISC-V VirtIO board";
|
||
|
|
mc->init = virt_machine_init;
|
||
|
|
mc->max_cpus = 8;
|
||
|
|
mc->default_cpu_type = VIRT_CPU;
|
||
|
|
mc->pci_allow_0_address = true;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const TypeInfo virt_machine_typeinfo = {
|
||
|
|
.name = MACHINE_TYPE_NAME("virt"),
|
||
|
|
.parent = TYPE_MACHINE,
|
||
|
|
.class_init = virt_machine_class_init,
|
||
|
|
.instance_init = virt_machine_instance_init,
|
||
|
|
.instance_size = sizeof(RISCVVirtState),
|
||
|
|
};
|
||
|
|
|
||
|
|
static void virt_machine_init_register_types(void)
|
||
|
|
{
|
||
|
|
type_register_static(&virt_machine_typeinfo);
|
||
|
|
}
|
||
|
|
|
||
|
|
type_init(virt_machine_init_register_types)
|