233 lines
8.1 KiB
C
233 lines
8.1 KiB
C
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/*
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* ARM SSE (Subsystems for Embedded): IoTKit, SSE-200
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*
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* Copyright (c) 2018 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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/*
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* This is a model of the Arm "Subsystems for Embedded" family of
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* hardware, which include the IoT Kit and the SSE-050, SSE-100 and
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* SSE-200. Currently we model:
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* - the Arm IoT Kit which is documented in
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* http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
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* - the SSE-200 which is documented in
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* http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
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*
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* The IoTKit contains:
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* a Cortex-M33
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* the IDAU
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* some timers and watchdogs
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* two peripheral protection controllers
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* a memory protection controller
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* a security controller
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* a bus fabric which arranges that some parts of the address
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* space are secure and non-secure aliases of each other
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* The SSE-200 additionally contains:
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* a second Cortex-M33
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* two Message Handling Units (MHUs)
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* an optional CryptoCell (which we do not model)
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* more SRAM banks with associated MPCs
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* multiple Power Policy Units (PPUs)
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* a control interface for an icache for each CPU
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* per-CPU identity and control register blocks
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*
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* QEMU interface:
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* + QOM property "memory" is a MemoryRegion containing the devices provided
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* by the board model.
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* + QOM property "MAINCLK" is the frequency of the main system clock
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* + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts.
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* (In hardware, the SSE-200 permits the number of expansion interrupts
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* for the two CPUs to be configured separately, but we restrict it to
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* being the same for both, to avoid having to have separate Property
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* lists for different variants. This restriction can be relaxed later
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* if necessary.)
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* + QOM property "SRAM_ADDR_WIDTH" sets the number of bits used for the
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* address of each SRAM bank (and thus the total amount of internal SRAM)
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* + QOM property "init-svtor" sets the initial value of the CPU SVTOR register
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* (where it expects to load the PC and SP from the vector table on reset)
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* + QOM properties "CPU0_FPU", "CPU0_DSP", "CPU1_FPU" and "CPU1_DSP" which
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* set whether the CPUs have the FPU and DSP features present. The default
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* (matching the hardware) is that for CPU0 in an IoTKit and CPU1 in an
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* SSE-200 both are present; CPU0 in an SSE-200 has neither.
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* Since the IoTKit has only one CPU, it does not have the CPU1_* properties.
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* + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CPU 0,
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* which are wired to its NVIC lines 32 .. n+32
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* + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts for
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* CPU 1, which are wired to its NVIC lines 32 .. n+32
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* + sysbus MMIO region 0 is the "AHB Slave Expansion" which allows
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* bus master devices in the board model to make transactions into
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* all the devices and memory areas in the IoTKit
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* Controlling up to 4 AHB expansion PPBs which a system using the IoTKit
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* might provide:
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* + named GPIO outputs apb_ppcexp{0,1,2,3}_nonsec[0..15]
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* + named GPIO outputs apb_ppcexp{0,1,2,3}_ap[0..15]
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* + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_enable
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* + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_clear
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* + named GPIO inputs apb_ppcexp{0,1,2,3}_irq_status
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* Controlling each of the 4 expansion AHB PPCs which a system using the IoTKit
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* might provide:
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* + named GPIO outputs ahb_ppcexp{0,1,2,3}_nonsec[0..15]
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* + named GPIO outputs ahb_ppcexp{0,1,2,3}_ap[0..15]
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* + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable
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* + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear
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* + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status
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* Controlling each of the 16 expansion MPCs which a system using the IoTKit
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* might provide:
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* + named GPIO inputs mpcexp_status[0..15]
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* Controlling each of the 16 expansion MSCs which a system using the IoTKit
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* might provide:
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* + named GPIO inputs mscexp_status[0..15]
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* + named GPIO outputs mscexp_clear[0..15]
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* + named GPIO outputs mscexp_ns[0..15]
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*/
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#ifndef ARMSSE_H
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#define ARMSSE_H
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#include "hw/sysbus.h"
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#include "hw/arm/armv7m.h"
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#include "hw/misc/iotkit-secctl.h"
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#include "hw/misc/tz-ppc.h"
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#include "hw/misc/tz-mpc.h"
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#include "hw/timer/cmsdk-apb-timer.h"
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#include "hw/timer/cmsdk-apb-dualtimer.h"
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#include "hw/watchdog/cmsdk-apb-watchdog.h"
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#include "hw/misc/iotkit-sysctl.h"
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#include "hw/misc/iotkit-sysinfo.h"
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#include "hw/misc/armsse-cpuid.h"
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#include "hw/misc/armsse-mhu.h"
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#include "hw/misc/unimp.h"
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#include "hw/or-irq.h"
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#include "hw/core/split-irq.h"
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#include "hw/cpu/cluster.h"
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#define TYPE_ARMSSE "arm-sse"
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#define ARMSSE(obj) OBJECT_CHECK(ARMSSE, (obj), TYPE_ARMSSE)
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/*
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* These type names are for specific IoTKit subsystems; other than
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* instantiating them, code using these devices should always handle
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* them via the ARMSSE base class, so they have no IOTKIT() etc macros.
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*/
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#define TYPE_IOTKIT "iotkit"
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#define TYPE_SSE200 "sse-200"
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/* We have an IRQ splitter and an OR gate input for each external PPC
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* and the 2 internal PPCs
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*/
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#define NUM_EXTERNAL_PPCS (IOTS_NUM_AHB_EXP_PPC + IOTS_NUM_APB_EXP_PPC)
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#define NUM_PPCS (NUM_EXTERNAL_PPCS + 2)
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#define MAX_SRAM_BANKS 4
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#if MAX_SRAM_BANKS > IOTS_NUM_MPC
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#error Too many SRAM banks
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#endif
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#define SSE_MAX_CPUS 2
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/* These define what each PPU in the ppu[] index is for */
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#define CPU0CORE_PPU 0
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#define CPU1CORE_PPU 1
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#define DBG_PPU 2
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#define RAM0_PPU 3
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#define RAM1_PPU 4
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#define RAM2_PPU 5
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#define RAM3_PPU 6
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#define NUM_PPUS 7
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typedef struct ARMSSE {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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ARMv7MState armv7m[SSE_MAX_CPUS];
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CPUClusterState cluster[SSE_MAX_CPUS];
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IoTKitSecCtl secctl;
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TZPPC apb_ppc0;
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TZPPC apb_ppc1;
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TZMPC mpc[IOTS_NUM_MPC];
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CMSDKAPBTIMER timer0;
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CMSDKAPBTIMER timer1;
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CMSDKAPBTIMER s32ktimer;
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qemu_or_irq ppc_irq_orgate;
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SplitIRQ sec_resp_splitter;
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SplitIRQ ppc_irq_splitter[NUM_PPCS];
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SplitIRQ mpc_irq_splitter[IOTS_NUM_EXP_MPC + IOTS_NUM_MPC];
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qemu_or_irq mpc_irq_orgate;
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qemu_or_irq nmi_orgate;
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SplitIRQ cpu_irq_splitter[32];
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CMSDKAPBDualTimer dualtimer;
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CMSDKAPBWatchdog s32kwatchdog;
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CMSDKAPBWatchdog nswatchdog;
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CMSDKAPBWatchdog swatchdog;
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IoTKitSysCtl sysctl;
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IoTKitSysCtl sysinfo;
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ARMSSEMHU mhu[2];
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UnimplementedDeviceState ppu[NUM_PPUS];
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UnimplementedDeviceState cachectrl[SSE_MAX_CPUS];
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UnimplementedDeviceState cpusecctrl[SSE_MAX_CPUS];
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ARMSSECPUID cpuid[SSE_MAX_CPUS];
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/*
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* 'container' holds all devices seen by all CPUs.
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* 'cpu_container[i]' is the view that CPU i has: this has the
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* per-CPU devices of that CPU, plus as the background 'container'
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* (or an alias of it, since we can only use it directly once).
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* container_alias[i] is the alias of 'container' used by CPU i+1;
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* CPU 0 can use 'container' directly.
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*/
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MemoryRegion container;
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MemoryRegion container_alias[SSE_MAX_CPUS - 1];
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MemoryRegion cpu_container[SSE_MAX_CPUS];
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MemoryRegion alias1;
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MemoryRegion alias2;
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MemoryRegion alias3[SSE_MAX_CPUS];
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MemoryRegion sram[MAX_SRAM_BANKS];
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qemu_irq *exp_irqs[SSE_MAX_CPUS];
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qemu_irq ppc0_irq;
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qemu_irq ppc1_irq;
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qemu_irq sec_resp_cfg;
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qemu_irq sec_resp_cfg_in;
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qemu_irq nsc_cfg_in;
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qemu_irq irq_status_in[NUM_EXTERNAL_PPCS];
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qemu_irq mpcexp_status_in[IOTS_NUM_EXP_MPC];
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uint32_t nsccfg;
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/* Properties */
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MemoryRegion *board_memory;
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uint32_t exp_numirq;
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uint32_t mainclk_frq;
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uint32_t sram_addr_width;
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uint32_t init_svtor;
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bool cpu_fpu[SSE_MAX_CPUS];
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bool cpu_dsp[SSE_MAX_CPUS];
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} ARMSSE;
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typedef struct ARMSSEInfo ARMSSEInfo;
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typedef struct ARMSSEClass {
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DeviceClass parent_class;
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const ARMSSEInfo *info;
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} ARMSSEClass;
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#define ARMSSE_CLASS(klass) \
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OBJECT_CLASS_CHECK(ARMSSEClass, (klass), TYPE_ARMSSE)
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#define ARMSSE_GET_CLASS(obj) \
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OBJECT_GET_CLASS(ARMSSEClass, (obj), TYPE_ARMSSE)
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#endif
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