204 lines
6.2 KiB
C
204 lines
6.2 KiB
C
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/*
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* QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
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*
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* PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
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*
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* Copyright (c) 2010,2011 David Gibson, IBM Corporation.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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*/
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#ifndef XICS_H
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#define XICS_H
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#include "exec/memory.h"
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#include "hw/qdev-core.h"
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#define XICS_IPI 0x2
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#define XICS_BUID 0x1
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#define XICS_IRQ_BASE (XICS_BUID << 12)
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/*
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* We currently only support one BUID which is our interrupt base
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* (the kernel implementation supports more but we don't exploit
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* that yet)
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*/
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typedef struct ICPStateClass ICPStateClass;
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typedef struct ICPState ICPState;
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typedef struct PnvICPState PnvICPState;
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typedef struct ICSStateClass ICSStateClass;
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typedef struct ICSState ICSState;
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typedef struct ICSIRQState ICSIRQState;
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typedef struct XICSFabric XICSFabric;
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#define TYPE_ICP "icp"
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#define ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_ICP)
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#define TYPE_PNV_ICP "pnv-icp"
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#define PNV_ICP(obj) OBJECT_CHECK(PnvICPState, (obj), TYPE_PNV_ICP)
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#define ICP_CLASS(klass) \
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OBJECT_CLASS_CHECK(ICPStateClass, (klass), TYPE_ICP)
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#define ICP_GET_CLASS(obj) \
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OBJECT_GET_CLASS(ICPStateClass, (obj), TYPE_ICP)
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struct ICPStateClass {
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DeviceClass parent_class;
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DeviceRealize parent_realize;
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};
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struct ICPState {
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/*< private >*/
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DeviceState parent_obj;
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/*< public >*/
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CPUState *cs;
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ICSState *xirr_owner;
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uint32_t xirr;
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uint8_t pending_priority;
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uint8_t mfrr;
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qemu_irq output;
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XICSFabric *xics;
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};
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#define ICP_PROP_XICS "xics"
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#define ICP_PROP_CPU "cpu"
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struct PnvICPState {
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ICPState parent_obj;
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MemoryRegion mmio;
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uint32_t links[3];
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};
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#define TYPE_ICS "ics"
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#define ICS(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS)
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#define ICS_CLASS(klass) \
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OBJECT_CLASS_CHECK(ICSStateClass, (klass), TYPE_ICS)
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#define ICS_GET_CLASS(obj) \
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OBJECT_GET_CLASS(ICSStateClass, (obj), TYPE_ICS)
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struct ICSStateClass {
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DeviceClass parent_class;
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DeviceRealize parent_realize;
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DeviceReset parent_reset;
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void (*reject)(ICSState *s, uint32_t irq);
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void (*resend)(ICSState *s);
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};
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struct ICSState {
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/*< private >*/
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DeviceState parent_obj;
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/*< public >*/
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uint32_t nr_irqs;
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uint32_t offset;
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ICSIRQState *irqs;
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XICSFabric *xics;
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};
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#define ICS_PROP_XICS "xics"
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static inline bool ics_valid_irq(ICSState *ics, uint32_t nr)
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{
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return (nr >= ics->offset) && (nr < (ics->offset + ics->nr_irqs));
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}
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struct ICSIRQState {
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uint32_t server;
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uint8_t priority;
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uint8_t saved_priority;
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#define XICS_STATUS_ASSERTED 0x1
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#define XICS_STATUS_SENT 0x2
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#define XICS_STATUS_REJECTED 0x4
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#define XICS_STATUS_MASKED_PENDING 0x8
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#define XICS_STATUS_PRESENTED 0x10
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#define XICS_STATUS_QUEUED 0x20
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uint8_t status;
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/* (flags & XICS_FLAGS_IRQ_MASK) == 0 means the interrupt is not allocated */
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#define XICS_FLAGS_IRQ_LSI 0x1
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#define XICS_FLAGS_IRQ_MSI 0x2
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#define XICS_FLAGS_IRQ_MASK 0x3
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uint8_t flags;
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};
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#define TYPE_XICS_FABRIC "xics-fabric"
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#define XICS_FABRIC(obj) \
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INTERFACE_CHECK(XICSFabric, (obj), TYPE_XICS_FABRIC)
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#define XICS_FABRIC_CLASS(klass) \
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OBJECT_CLASS_CHECK(XICSFabricClass, (klass), TYPE_XICS_FABRIC)
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#define XICS_FABRIC_GET_CLASS(obj) \
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OBJECT_GET_CLASS(XICSFabricClass, (obj), TYPE_XICS_FABRIC)
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typedef struct XICSFabricClass {
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InterfaceClass parent;
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ICSState *(*ics_get)(XICSFabric *xi, int irq);
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void (*ics_resend)(XICSFabric *xi);
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ICPState *(*icp_get)(XICSFabric *xi, int server);
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} XICSFabricClass;
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ICPState *xics_icp_get(XICSFabric *xi, int server);
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/* Internal XICS interfaces */
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void icp_set_cppr(ICPState *icp, uint8_t cppr);
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void icp_set_mfrr(ICPState *icp, uint8_t mfrr);
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uint32_t icp_accept(ICPState *ss);
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uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr);
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void icp_eoi(ICPState *icp, uint32_t xirr);
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void icp_irq(ICSState *ics, int server, int nr, uint8_t priority);
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void icp_reset(ICPState *icp);
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void ics_write_xive(ICSState *ics, int nr, int server,
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uint8_t priority, uint8_t saved_priority);
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void ics_set_irq(void *opaque, int srcno, int val);
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static inline bool ics_irq_free(ICSState *ics, uint32_t srcno)
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{
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return !(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK);
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}
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void ics_set_irq_type(ICSState *ics, int srcno, bool lsi);
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void icp_pic_print_info(ICPState *icp, Monitor *mon);
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void ics_pic_print_info(ICSState *ics, Monitor *mon);
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void ics_resend(ICSState *ics);
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void icp_resend(ICPState *ss);
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Object *icp_create(Object *cpu, const char *type, XICSFabric *xi,
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Error **errp);
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void icp_destroy(ICPState *icp);
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/* KVM */
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void icp_get_kvm_state(ICPState *icp);
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int icp_set_kvm_state(ICPState *icp, Error **errp);
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void icp_synchronize_state(ICPState *icp);
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void icp_kvm_realize(DeviceState *dev, Error **errp);
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void ics_get_kvm_state(ICSState *ics);
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int ics_set_kvm_state_one(ICSState *ics, int srcno, Error **errp);
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int ics_set_kvm_state(ICSState *ics, Error **errp);
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void ics_synchronize_state(ICSState *ics);
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void ics_kvm_set_irq(ICSState *ics, int srcno, int val);
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#endif /* XICS_H */
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