489 lines
18 KiB
C
489 lines
18 KiB
C
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/*
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* QEMU PowerPC XIVE interrupt controller model
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*
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*
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* The POWER9 processor comes with a new interrupt controller, called
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* XIVE as "eXternal Interrupt Virtualization Engine".
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*
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* = Overall architecture
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*
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*
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* XIVE Interrupt Controller
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* +------------------------------------+ IPIs
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* | +---------+ +---------+ +--------+ | +-------+
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* | |VC | |CQ | |PC |----> | CORES |
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* | | esb | | | | |----> | |
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* | | eas | | Bridge | | tctx |----> | |
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* | |SC end | | | | nvt | | | |
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* +------+ | +---------+ +----+----+ +--------+ | +-+-+-+-+
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* | RAM | +------------------|-----------------+ | | |
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* | | | | | |
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* | | | | | |
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* | | +--------------------v------------------------v-v-v--+ other
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* | <--+ Power Bus +--> chips
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* | esb | +---------+-----------------------+------------------+
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* | eas | | |
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* | end | +--|------+ |
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* | nvt | +----+----+ | +----+----+
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* +------+ |SC | | |SC |
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* | | | | |
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* | PQ-bits | | | PQ-bits |
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* | local |-+ | in VC |
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* +---------+ +---------+
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* PCIe NX,NPU,CAPI
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*
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* SC: Source Controller (aka. IVSE)
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* VC: Virtualization Controller (aka. IVRE)
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* PC: Presentation Controller (aka. IVPE)
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* CQ: Common Queue (Bridge)
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*
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* PQ-bits: 2 bits source state machine (P:pending Q:queued)
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* esb: Event State Buffer (Array of PQ bits in an IVSE)
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* eas: Event Assignment Structure
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* end: Event Notification Descriptor
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* nvt: Notification Virtual Target
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* tctx: Thread interrupt Context
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*
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*
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* The XIVE IC is composed of three sub-engines :
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*
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* - Interrupt Virtualization Source Engine (IVSE), or Source
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* Controller (SC). These are found in PCI PHBs, in the PSI host
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* bridge controller, but also inside the main controller for the
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* core IPIs and other sub-chips (NX, CAP, NPU) of the
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* chip/processor. They are configured to feed the IVRE with events.
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*
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* - Interrupt Virtualization Routing Engine (IVRE) or Virtualization
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* Controller (VC). Its job is to match an event source with an
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* Event Notification Descriptor (END).
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*
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* - Interrupt Virtualization Presentation Engine (IVPE) or
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* Presentation Controller (PC). It maintains the interrupt context
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* state of each thread and handles the delivery of the external
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* exception to the thread.
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*
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* In XIVE 1.0, the sub-engines used to be referred as:
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*
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* SC Source Controller
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* VC Virtualization Controller
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* PC Presentation Controller
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* CQ Common Queue (PowerBUS Bridge)
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*
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*
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* = XIVE internal tables
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*
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* Each of the sub-engines uses a set of tables to redirect exceptions
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* from event sources to CPU threads.
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*
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* +-------+
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* User or OS | EQ |
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* or +------>|entries|
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* Hypervisor | | .. |
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* Memory | +-------+
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* | ^
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* | |
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* +-------------------------------------------------+
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* | |
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* Hypervisor +------+ +---+--+ +---+--+ +------+
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* Memory | ESB | | EAT | | ENDT | | NVTT |
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* (skiboot) +----+-+ +----+-+ +----+-+ +------+
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* ^ | ^ | ^ | ^
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* | | | | | | |
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* +-------------------------------------------------+
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* | | | | | | |
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* | | | | | | |
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* +----|--|--------|--|--------|--|-+ +-|-----+ +------+
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* | | | | | | | | | | tctx| |Thread|
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* IPI or --> | + v + v + v |---| + .. |-----> |
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* HW events --> | | | | | |
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* IVSE | IVRE | | IVPE | +------+
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* +---------------------------------+ +-------+
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*
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*
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*
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* The IVSE have a 2-bits state machine, P for pending and Q for queued,
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* for each source that allows events to be triggered. They are stored in
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* an Event State Buffer (ESB) array and can be controlled by MMIOs.
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*
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* If the event is let through, the IVRE looks up in the Event Assignment
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* Structure (EAS) table for an Event Notification Descriptor (END)
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* configured for the source. Each Event Notification Descriptor defines
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* a notification path to a CPU and an in-memory Event Queue, in which
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* will be enqueued an EQ data for the OS to pull.
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*
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* The IVPE determines if a Notification Virtual Target (NVT) can
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* handle the event by scanning the thread contexts of the VCPUs
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* dispatched on the processor HW threads. It maintains the state of
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* the thread interrupt context (TCTX) of each thread in a NVT table.
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*
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* = Acronyms
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*
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* Description In XIVE 1.0, used to be referred as
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*
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* EAS Event Assignment Structure IVE Interrupt Virt. Entry
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* EAT Event Assignment Table IVT Interrupt Virt. Table
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* ENDT Event Notif. Descriptor Table EQDT Event Queue Desc. Table
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* EQ Event Queue same
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* ESB Event State Buffer SBE State Bit Entry
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* NVT Notif. Virtual Target VPD Virtual Processor Desc.
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* NVTT Notif. Virtual Target Table VPDT Virtual Processor Desc. Table
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* TCTX Thread interrupt Context
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*
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*
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* Copyright (c) 2017-2018, IBM Corporation.
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*
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* This code is licensed under the GPL version 2 or later. See the
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* COPYING file in the top-level directory.
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*
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*/
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#ifndef PPC_XIVE_H
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#define PPC_XIVE_H
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#include "sysemu/kvm.h"
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#include "hw/sysbus.h"
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#include "hw/ppc/xive_regs.h"
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/*
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* XIVE Notifier (Interface between Source and Router)
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*/
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typedef struct XiveNotifier XiveNotifier;
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#define TYPE_XIVE_NOTIFIER "xive-notifier"
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#define XIVE_NOTIFIER(obj) \
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INTERFACE_CHECK(XiveNotifier, (obj), TYPE_XIVE_NOTIFIER)
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#define XIVE_NOTIFIER_CLASS(klass) \
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OBJECT_CLASS_CHECK(XiveNotifierClass, (klass), TYPE_XIVE_NOTIFIER)
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#define XIVE_NOTIFIER_GET_CLASS(obj) \
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OBJECT_GET_CLASS(XiveNotifierClass, (obj), TYPE_XIVE_NOTIFIER)
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typedef struct XiveNotifierClass {
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InterfaceClass parent;
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void (*notify)(XiveNotifier *xn, uint32_t lisn);
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} XiveNotifierClass;
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/*
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* XIVE Interrupt Source
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*/
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#define TYPE_XIVE_SOURCE "xive-source"
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#define XIVE_SOURCE(obj) OBJECT_CHECK(XiveSource, (obj), TYPE_XIVE_SOURCE)
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/*
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* XIVE Interrupt Source characteristics, which define how the ESB are
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* controlled.
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*/
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#define XIVE_SRC_H_INT_ESB 0x1 /* ESB managed with hcall H_INT_ESB */
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#define XIVE_SRC_STORE_EOI 0x2 /* Store EOI supported */
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typedef struct XiveSource {
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DeviceState parent;
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/* IRQs */
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uint32_t nr_irqs;
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unsigned long *lsi_map;
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/* PQ bits and LSI assertion bit */
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uint8_t *status;
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/* ESB memory region */
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uint64_t esb_flags;
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uint32_t esb_shift;
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MemoryRegion esb_mmio;
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/* KVM support */
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void *esb_mmap;
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MemoryRegion esb_mmio_kvm;
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XiveNotifier *xive;
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} XiveSource;
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/*
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* ESB MMIO setting. Can be one page, for both source triggering and
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* source management, or two different pages. See below for magic
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* values.
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*/
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#define XIVE_ESB_4K 12 /* PSI HB only */
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#define XIVE_ESB_4K_2PAGE 13
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#define XIVE_ESB_64K 16
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#define XIVE_ESB_64K_2PAGE 17
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static inline bool xive_source_esb_has_2page(XiveSource *xsrc)
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{
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return xsrc->esb_shift == XIVE_ESB_64K_2PAGE ||
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xsrc->esb_shift == XIVE_ESB_4K_2PAGE;
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}
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/* The trigger page is always the first/even page */
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static inline hwaddr xive_source_esb_page(XiveSource *xsrc, uint32_t srcno)
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{
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assert(srcno < xsrc->nr_irqs);
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return (1ull << xsrc->esb_shift) * srcno;
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}
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/* In a two pages ESB MMIO setting, the odd page is for management */
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static inline hwaddr xive_source_esb_mgmt(XiveSource *xsrc, int srcno)
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{
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hwaddr addr = xive_source_esb_page(xsrc, srcno);
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if (xive_source_esb_has_2page(xsrc)) {
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addr += (1 << (xsrc->esb_shift - 1));
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}
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return addr;
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}
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/*
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* Each interrupt source has a 2-bit state machine which can be
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* controlled by MMIO. P indicates that an interrupt is pending (has
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* been sent to a queue and is waiting for an EOI). Q indicates that
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* the interrupt has been triggered while pending.
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*
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* This acts as a coalescing mechanism in order to guarantee that a
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* given interrupt only occurs at most once in a queue.
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*
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* When doing an EOI, the Q bit will indicate if the interrupt
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* needs to be re-triggered.
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*/
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#define XIVE_STATUS_ASSERTED 0x4 /* Extra bit for LSI */
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#define XIVE_ESB_VAL_P 0x2
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#define XIVE_ESB_VAL_Q 0x1
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#define XIVE_ESB_RESET 0x0
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#define XIVE_ESB_PENDING XIVE_ESB_VAL_P
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#define XIVE_ESB_QUEUED (XIVE_ESB_VAL_P | XIVE_ESB_VAL_Q)
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#define XIVE_ESB_OFF XIVE_ESB_VAL_Q
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/*
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* "magic" Event State Buffer (ESB) MMIO offsets.
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*
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* The following offsets into the ESB MMIO allow to read or manipulate
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* the PQ bits. They must be used with an 8-byte load instruction.
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* They all return the previous state of the interrupt (atomically).
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*
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* Additionally, some ESB pages support doing an EOI via a store and
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* some ESBs support doing a trigger via a separate trigger page.
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*/
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#define XIVE_ESB_STORE_EOI 0x400 /* Store */
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#define XIVE_ESB_LOAD_EOI 0x000 /* Load */
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#define XIVE_ESB_GET 0x800 /* Load */
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#define XIVE_ESB_SET_PQ_00 0xc00 /* Load */
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#define XIVE_ESB_SET_PQ_01 0xd00 /* Load */
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#define XIVE_ESB_SET_PQ_10 0xe00 /* Load */
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#define XIVE_ESB_SET_PQ_11 0xf00 /* Load */
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uint8_t xive_source_esb_get(XiveSource *xsrc, uint32_t srcno);
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uint8_t xive_source_esb_set(XiveSource *xsrc, uint32_t srcno, uint8_t pq);
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void xive_source_pic_print_info(XiveSource *xsrc, uint32_t offset,
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Monitor *mon);
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static inline bool xive_source_irq_is_lsi(XiveSource *xsrc, uint32_t srcno)
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{
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assert(srcno < xsrc->nr_irqs);
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return test_bit(srcno, xsrc->lsi_map);
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}
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static inline void xive_source_irq_set_lsi(XiveSource *xsrc, uint32_t srcno)
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{
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assert(srcno < xsrc->nr_irqs);
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bitmap_set(xsrc->lsi_map, srcno, 1);
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}
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void xive_source_set_irq(void *opaque, int srcno, int val);
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/*
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* XIVE Thread interrupt Management (TM) context
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*/
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#define TYPE_XIVE_TCTX "xive-tctx"
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#define XIVE_TCTX(obj) OBJECT_CHECK(XiveTCTX, (obj), TYPE_XIVE_TCTX)
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/*
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* XIVE Thread interrupt Management register rings :
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*
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* QW-0 User event-based exception state
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* QW-1 O/S OS context for priority management, interrupt acks
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* QW-2 Pool hypervisor pool context for virtual processors dispatched
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* QW-3 Physical physical thread context and security context
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*/
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#define XIVE_TM_RING_COUNT 4
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#define XIVE_TM_RING_SIZE 0x10
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typedef struct XivePresenter XivePresenter;
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typedef struct XiveTCTX {
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DeviceState parent_obj;
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CPUState *cs;
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qemu_irq hv_output;
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qemu_irq os_output;
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uint8_t regs[XIVE_TM_RING_COUNT * XIVE_TM_RING_SIZE];
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XivePresenter *xptr;
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} XiveTCTX;
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/*
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* XIVE Router
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*/
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typedef struct XiveFabric XiveFabric;
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typedef struct XiveRouter {
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SysBusDevice parent;
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XiveFabric *xfb;
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} XiveRouter;
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#define TYPE_XIVE_ROUTER "xive-router"
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#define XIVE_ROUTER(obj) \
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OBJECT_CHECK(XiveRouter, (obj), TYPE_XIVE_ROUTER)
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#define XIVE_ROUTER_CLASS(klass) \
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OBJECT_CLASS_CHECK(XiveRouterClass, (klass), TYPE_XIVE_ROUTER)
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#define XIVE_ROUTER_GET_CLASS(obj) \
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OBJECT_GET_CLASS(XiveRouterClass, (obj), TYPE_XIVE_ROUTER)
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typedef struct XiveRouterClass {
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SysBusDeviceClass parent;
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/* XIVE table accessors */
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int (*get_eas)(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx,
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XiveEAS *eas);
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int (*get_end)(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
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XiveEND *end);
|
||
|
|
int (*write_end)(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
|
||
|
|
XiveEND *end, uint8_t word_number);
|
||
|
|
int (*get_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
|
||
|
|
XiveNVT *nvt);
|
||
|
|
int (*write_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
|
||
|
|
XiveNVT *nvt, uint8_t word_number);
|
||
|
|
uint8_t (*get_block_id)(XiveRouter *xrtr);
|
||
|
|
} XiveRouterClass;
|
||
|
|
|
||
|
|
int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx,
|
||
|
|
XiveEAS *eas);
|
||
|
|
int xive_router_get_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
|
||
|
|
XiveEND *end);
|
||
|
|
int xive_router_write_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
|
||
|
|
XiveEND *end, uint8_t word_number);
|
||
|
|
int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
|
||
|
|
XiveNVT *nvt);
|
||
|
|
int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
|
||
|
|
XiveNVT *nvt, uint8_t word_number);
|
||
|
|
void xive_router_notify(XiveNotifier *xn, uint32_t lisn);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* XIVE Presenter
|
||
|
|
*/
|
||
|
|
|
||
|
|
typedef struct XiveTCTXMatch {
|
||
|
|
XiveTCTX *tctx;
|
||
|
|
uint8_t ring;
|
||
|
|
} XiveTCTXMatch;
|
||
|
|
|
||
|
|
#define TYPE_XIVE_PRESENTER "xive-presenter"
|
||
|
|
#define XIVE_PRESENTER(obj) \
|
||
|
|
INTERFACE_CHECK(XivePresenter, (obj), TYPE_XIVE_PRESENTER)
|
||
|
|
#define XIVE_PRESENTER_CLASS(klass) \
|
||
|
|
OBJECT_CLASS_CHECK(XivePresenterClass, (klass), TYPE_XIVE_PRESENTER)
|
||
|
|
#define XIVE_PRESENTER_GET_CLASS(obj) \
|
||
|
|
OBJECT_GET_CLASS(XivePresenterClass, (obj), TYPE_XIVE_PRESENTER)
|
||
|
|
|
||
|
|
typedef struct XivePresenterClass {
|
||
|
|
InterfaceClass parent;
|
||
|
|
int (*match_nvt)(XivePresenter *xptr, uint8_t format,
|
||
|
|
uint8_t nvt_blk, uint32_t nvt_idx,
|
||
|
|
bool cam_ignore, uint8_t priority,
|
||
|
|
uint32_t logic_serv, XiveTCTXMatch *match);
|
||
|
|
} XivePresenterClass;
|
||
|
|
|
||
|
|
int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
|
||
|
|
uint8_t format,
|
||
|
|
uint8_t nvt_blk, uint32_t nvt_idx,
|
||
|
|
bool cam_ignore, uint32_t logic_serv);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* XIVE Fabric (Interface between Interrupt Controller and Machine)
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define TYPE_XIVE_FABRIC "xive-fabric"
|
||
|
|
#define XIVE_FABRIC(obj) \
|
||
|
|
INTERFACE_CHECK(XiveFabric, (obj), TYPE_XIVE_FABRIC)
|
||
|
|
#define XIVE_FABRIC_CLASS(klass) \
|
||
|
|
OBJECT_CLASS_CHECK(XiveFabricClass, (klass), TYPE_XIVE_FABRIC)
|
||
|
|
#define XIVE_FABRIC_GET_CLASS(obj) \
|
||
|
|
OBJECT_GET_CLASS(XiveFabricClass, (obj), TYPE_XIVE_FABRIC)
|
||
|
|
|
||
|
|
typedef struct XiveFabricClass {
|
||
|
|
InterfaceClass parent;
|
||
|
|
int (*match_nvt)(XiveFabric *xfb, uint8_t format,
|
||
|
|
uint8_t nvt_blk, uint32_t nvt_idx,
|
||
|
|
bool cam_ignore, uint8_t priority,
|
||
|
|
uint32_t logic_serv, XiveTCTXMatch *match);
|
||
|
|
} XiveFabricClass;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* XIVE END ESBs
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define TYPE_XIVE_END_SOURCE "xive-end-source"
|
||
|
|
#define XIVE_END_SOURCE(obj) \
|
||
|
|
OBJECT_CHECK(XiveENDSource, (obj), TYPE_XIVE_END_SOURCE)
|
||
|
|
|
||
|
|
typedef struct XiveENDSource {
|
||
|
|
DeviceState parent;
|
||
|
|
|
||
|
|
uint32_t nr_ends;
|
||
|
|
|
||
|
|
/* ESB memory region */
|
||
|
|
uint32_t esb_shift;
|
||
|
|
MemoryRegion esb_mmio;
|
||
|
|
|
||
|
|
XiveRouter *xrtr;
|
||
|
|
} XiveENDSource;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* For legacy compatibility, the exceptions define up to 256 different
|
||
|
|
* priorities. P9 implements only 9 levels : 8 active levels [0 - 7]
|
||
|
|
* and the least favored level 0xFF.
|
||
|
|
*/
|
||
|
|
#define XIVE_PRIORITY_MAX 7
|
||
|
|
|
||
|
|
/*
|
||
|
|
* XIVE Thread Interrupt Management Aera (TIMA)
|
||
|
|
*
|
||
|
|
* This region gives access to the registers of the thread interrupt
|
||
|
|
* management context. It is four page wide, each page providing a
|
||
|
|
* different view of the registers. The page with the lower offset is
|
||
|
|
* the most privileged and gives access to the entire context.
|
||
|
|
*/
|
||
|
|
#define XIVE_TM_HW_PAGE 0x0
|
||
|
|
#define XIVE_TM_HV_PAGE 0x1
|
||
|
|
#define XIVE_TM_OS_PAGE 0x2
|
||
|
|
#define XIVE_TM_USER_PAGE 0x3
|
||
|
|
|
||
|
|
void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
|
||
|
|
uint64_t value, unsigned size);
|
||
|
|
uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
|
||
|
|
unsigned size);
|
||
|
|
|
||
|
|
void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon);
|
||
|
|
Object *xive_tctx_create(Object *cpu, XivePresenter *xptr, Error **errp);
|
||
|
|
void xive_tctx_reset(XiveTCTX *tctx);
|
||
|
|
void xive_tctx_destroy(XiveTCTX *tctx);
|
||
|
|
void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* KVM XIVE device helpers
|
||
|
|
*/
|
||
|
|
|
||
|
|
int kvmppc_xive_source_reset_one(XiveSource *xsrc, int srcno, Error **errp);
|
||
|
|
void kvmppc_xive_source_set_irq(void *opaque, int srcno, int val);
|
||
|
|
void kvmppc_xive_cpu_connect(XiveTCTX *tctx, Error **errp);
|
||
|
|
void kvmppc_xive_cpu_synchronize_state(XiveTCTX *tctx, Error **errp);
|
||
|
|
void kvmppc_xive_cpu_get_state(XiveTCTX *tctx, Error **errp);
|
||
|
|
void kvmppc_xive_cpu_set_state(XiveTCTX *tctx, Error **errp);
|
||
|
|
|
||
|
|
#endif /* PPC_XIVE_H */
|