324 lines
12 KiB
C
324 lines
12 KiB
C
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/******************************************************************************
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* Copyright (c) 2004, 2008 IBM Corporation
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* All rights reserved.
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* This program and the accompanying materials
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* are made available under the terms of the BSD License
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* which accompanies this distribution, and is available at
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* http://www.opensource.org/licenses/bsd-license.php
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*
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* Contributors:
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* IBM Corporation - initial implementation
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*****************************************************************************/
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#include <cache.h>
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#include <netdriver.h>
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// Debug switches
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//#define BCM_DEBUG // main debug switch, w/o it the other ones don't work
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//#define BCM_SHOW_RCV
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//#define BCM_SHOW_RCV_DATA
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//#define BCM_SHOW_XMIT
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//#define BCM_SHOW_XMIT_DATA
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//#define BCM_SHOW_XMIT_STATS
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//#define BCM_SHOW_IDX
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//#define BCM_SHOW_STATS
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//#define BCM_SHOW_ASF_REGS
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// Switch to enable SW AUTO-NEG
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// don't try, it's still incomplete
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//#define BCM_SW_AUTONEG
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/*
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* used register offsets
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*/
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// PCI command register
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#define PCI_COM_R ( (uint16_t) 0x0004 )
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// PCI Cache Line Size register
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#define PCI_CACHELS_R ( (uint16_t) 0x000c )
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// PCI bar1 register
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#define PCI_BAR1_R ( (uint16_t) 0x0010 )
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// PCI bar2 register
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#define PCI_BAR2_R ( (uint16_t) 0x0014 )
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// PCI bar1 register
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#define PCI_SUBID_R ( (uint16_t) 0x002e )
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// PCI-X Comand register
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#define PCI_X_COM_R ( (uint16_t) 0x0042 )
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// Message Data Register
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#define MSG_DATA_R ( (uint16_t) 0x0064 )
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// PCI misc host contrl register
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#define PCI_MISC_HCTRL_R ( (uint16_t) 0x0068 )
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// DMA Read/Write Control register
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#define DMA_RW_CTRL_R ( (uint16_t) 0x006c )
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// PCI State register
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#define PCI_STATE_R ( (uint16_t) 0x0070 )
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// PCI_Clock Control register
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#define PCI_CLK_CTRL_R ( (uint16_t) 0x0074 )
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// Register Base Address Register
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#define REG_BASE_ADDR_REG ( (uint16_t) 0x0078 )
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// Memory Window Base Address Register
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#define MEM_BASE_ADDR_REG ( (uint16_t) 0x007c )
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// Register Data Register
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#define REG_DATA_REG ( (uint16_t) 0x0080 )
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// Memory Window Data Register
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#define MEM_DATA_REG ( (uint16_t) 0x0084 )
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// MAC Function register
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#define MAC_FUNC_R ( (uint16_t) 0x00b8 )
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// Interrupt Mailbox 0 register
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#define INT_MBX0_R ( (uint16_t) 0x0204 )
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// Ethernet MAC Mode register
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#define ETH_MAC_MODE_R ( (uint16_t) 0x0400 )
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// Ethernet MAC Addresses registers
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#define MAC_ADDR_OFFS_HI( idx ) ( (uint16_t) ( (idx*2 + 0)*sizeof( uint32_t ) + 0x0410 ) )
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#define MAC_ADDR_OFFS_LO( idx ) ( (uint16_t) ( (idx*2 + 1)*sizeof( uint32_t ) + 0x0410 ) )
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// Ethernet MAC Status register
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#define ETH_MAC_STAT_R ( (uint16_t) 0x0404 )
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// Ethernet MAC Event Enable register
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#define ETH_MAC_EVT_EN_R ( (uint16_t) 0x0408 )
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// Ethernet Transmit Random Backoff register
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#define ETH_TX_RND_BO_R ( (uint16_t) 0x0438 )
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// Receive MTU Size register
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#define RX_MTU_SIZE_R ( (uint16_t) 0x043c )
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// Transmit 1000BASE-X Auto Negotiation register
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#define TX_1000BX_AUTONEG_R ( (uint16_t) 0x0444 )
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// Receive 1000BASE-X Auto Negotiation register
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#define RX_1000BX_AUTONEG_R ( (uint16_t) 0x0448 )
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// MI Communication register
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#define MI_COM_R ( (uint16_t) 0x044c )
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// MI Status Register
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#define MI_STATUS_R ( (uint16_t) 0x0450 )
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// MI Mode register
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#define MI_MODE_R ( (uint16_t) 0x0454 )
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// Transmit MAC Mode register
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#define TX_MAC_MODE_R ( (uint16_t) 0x045c )
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// Transmit MAC Length register
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#define TX_MAC_LEN_R ( (uint16_t) 0x0464 )
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// Receive MAC Mode register
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#define RX_MAC_MODE_R ( (uint16_t) 0x0468 )
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// MAC Hash 0 register* VPD Config:
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#define MAC_HASH0_R ( (uint16_t) 0x0470 )
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// MAC Hash 1 register
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#define MAC_HASH1_R ( (uint16_t) 0x0474 )
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// MAC Hash 2 register
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#define MAC_HASH2_R ( (uint16_t) 0x0478 )
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// MAC Hash 3 register
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#define MAC_HASH3_R ( (uint16_t) 0x047c )
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// Receive Rules Control register
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#define RX_RULE_CTRL_R( idx ) ( (uint16_t) ( idx*8 + 0x0480 ) )
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// Receive Rules Value register
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#define RX_RULE_VAL_R( idx ) ( (uint16_t) ( idx*8 + 0x0484 ) )
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// Receive Rules Configuration register
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#define RX_RULE_CFG_R ( (uint16_t) 0x0500 )
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// Low Watermark Max Receive Frames register
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#define LOW_WMARK_MAX_RXFRAM_R ( (uint16_t) 0x0504 )
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// SerDes Control Register
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#define SERDES_CTRL_R ( (uint16_t) 0x0590 )
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// Hardware Auto Negotiation Control Register
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#define HW_AUTONEG_CTRL_R ( (uint16_t) 0x05B0 )
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// Hardware Auto Negotiation Status Register
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#define HW_AUTONEG_STAT_R ( (uint16_t) 0x05B4 )
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// Send Data Initiator Mode register
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#define TX_DAT_INIT_MODE_R ( (uint16_t) 0x0c00 )
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// Send Data Completion Mode register
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#define TX_DAT_COMPL_MODE_R ( (uint16_t) 0x1000 )
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// Send BD Ring Selector Mode register
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#define TX_BD_RING_SEL_MODE_R ( (uint16_t) 0x1400 )
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// Send BD Initiator Mode register
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#define TX_BD_INIT_MODE_R ( (uint16_t) 0x1800 )
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// Send BD Completion Mode register
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#define TX_BD_COMPL_MODE_R ( (uint16_t) 0x1c00 )
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// Receive List Placement Mode register
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#define RX_LST_PLACE_MODE_R ( (uint16_t) 0x2000 )
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// Receive List Placement Configuration register
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#define RX_LST_PLACE_CFG_R ( (uint16_t) 0x2010 )
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// Receive List Placement Statistics Enable Mask register
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#define RX_LST_PLACE_STAT_EN_R ( (uint16_t) 0x2018 )
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// Receive Data & Receive BD Initiator Mode register
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#define RX_DAT_BD_INIT_MODE_R ( (uint16_t) 0x2400 )
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// Receive Data Completion Mode register
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#define RX_DAT_COMPL_MODE_R ( (uint16_t) 0x2800 )
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// Receive BD Initiator Mode register
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#define RX_BD_INIT_MODE_R ( (uint16_t) 0x2c00 )
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// Standard Receive Producer Ring Replenish Threshold register
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#define STD_RXPR_REP_THR_R ( (uint16_t) 0x2c18 )
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// Receive BD Completion Mode register
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#define RX_BD_COMPL_MODE_R ( (uint16_t) 0x3000 )
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// Receive List Selector Mode register
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#define RX_LST_SEL_MODE_R ( (uint16_t) 0x3400 )
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// MBUF Cluster Free Mode register
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#define MBUF_CLSTR_FREE_MODE_R ( (uint16_t) 0x3800 )
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// Host Coalescing Mode register
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#define HOST_COAL_MODE_R ( (uint16_t) 0x3c00 )
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// Receive Coalescing Ticks register
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#define RX_COAL_TICKS_R ( (uint16_t) 0x3c08 )
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// Send Coalescing Ticks register
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#define TX_COAL_TICKS_R ( (uint16_t) 0x3c0c )
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// Receive Max Coalesced BD Count register
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#define RX_COAL_MAX_BD_R ( (uint16_t) 0x3c10 )
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// Send Max Coalesced BD Count register
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#define TX_COAL_MAX_BD_R ( (uint16_t) 0x3c14 )
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// Receive Coalescing Ticks During Int register
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#define RX_COAL_TICKS_INT_R ( (uint16_t) 0x3c18 )
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// Send Coalescing Ticks During Int register
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#define TX_COAL_TICKS_INT_R ( (uint16_t) 0x3c1c )
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// Receive Max Coalesced BD Count During Int register
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#define RX_COAL_MAX_BD_INT_R ( (uint16_t) 0x3c18 )
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// Send Max Coalesced BD Count During Int register
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#define TX_COAL_MAX_BD_INT_R ( (uint16_t) 0x3c1c )
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// Statistics Ticks Counter register
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#define STAT_TICK_CNT_R ( (uint16_t) 0x3c28 )
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// Status Block Host Address Low register
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#define STB_HOST_ADDR_HI_R ( (uint16_t) 0x3c38 )
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// Status Block Host Address High register
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#define STB_HOST_ADDR_LO_R ( (uint16_t) 0x3c3c )
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// Statistics Base Address register
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#define STAT_NIC_ADDR_R ( (uint16_t) 0x3c40 )
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// Status Block Base Address register
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#define STB_NIC_ADDR_R ( (uint16_t) 0x3c44 )
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// Memory Arbiter Mode register
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#define MEMARB_MODE_R ( (uint16_t) 0x4000 )
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// Buffer Manager Mode register
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#define BUF_MAN_MODE_R ( (uint16_t) 0x4400 )
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// MBuf Pool Address register
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#define MBUF_POOL_ADDR_R ( (uint16_t) 0x4408 )
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// MBuf Pool Length register
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#define MBUF_POOL_LEN_R ( (uint16_t) 0x440c )
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// Read DMA Mbuf Low Watermark register
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#define DMA_RMBUF_LOW_WMARK_R ( (uint16_t) 0x4410 )
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// MAC Rx Mbuf Low Watermark register
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#define MAC_RXMBUF_LOW_WMARK_R ( (uint16_t) 0x4414 )
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// Mbuf High Watermark register
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#define MBUF_HIGH_WMARK_R ( (uint16_t) 0x4418 )
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// DMA Descriptor Pool Address register
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#define DMA_DESC_POOL_ADDR_R ( (uint16_t) 0x442c )
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// DMA Descriptor Pool Length register
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#define DMA_DESC_POOL_LEN_R ( (uint16_t) 0x4430 )
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// DMA Descriptor Low Watermark register
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#define DMA_DESC_LOW_WM_R ( (uint16_t) 0x4434 )
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// DMA Descriptor HIGH Watermark register
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#define DMA_DESC_HIGH_WM_R ( (uint16_t) 0x4438 )
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// Read DMA Mode register
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#define RD_DMA_MODE_R ( (uint16_t) 0x4800 )
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// Write DMA Mode register
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#define WR_DMA_MODE_R ( (uint16_t) 0x4c00 )
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// FTQ Reset register
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#define FTQ_RES_R ( (uint16_t) 0x5c00 )
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// MSI Mode register
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#define MSI_MODE_R ( (uint16_t) 0x6000 )
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// DMA completion Mode register
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#define DMA_COMPL_MODE_R ( (uint16_t) 0x6400 )
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// Mode Control register
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#define MODE_CTRL_R ( (uint16_t) 0x6800 )
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// Misc Configuration register
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#define MISC_CFG_R ( (uint16_t) 0x6804 )
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// Misc Local Control register
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#define MISC_LOCAL_CTRL_R ( (uint16_t) 0x6808 )
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// RX-Risc Mode Register
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#define RX_CPU_MODE_R ( (uint16_t) 0x5000 )
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// RX-Risc State Register
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#define RX_CPU_STATE_R ( (uint16_t) 0x5004 )
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// RX-Risc Program Counter
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#define RX_CPU_PC_R ( (uint16_t) 0x501c )
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// RX-Risc Event Register
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#define RX_CPU_EVENT_R ( (uint16_t) 0x6810 )
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// MDI Control register
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#define MDI_CTRL_R ( (uint16_t) 0x6844 )
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// WOL Mode register
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#define WOL_MODE_R ( (uint16_t) 0x6880 )
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// WOL Config register
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#define WOL_CFG_R ( (uint16_t) 0x6884 )
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// WOL Status register
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#define WOL_STATUS_R ( (uint16_t) 0x6888 )
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// ASF Control register
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#define ASF_CTRL_R ( (uint16_t) 0x6c00 )
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// ASF Watchdog Timer register
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#define ASF_WATCHDOG_TIMER_R ( (uint16_t) 0x6c0c )
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// ASF Heartbeat Timer register
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#define ASF_HEARTBEAT_TIMER_R ( (uint16_t) 0x6c10 )
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// Poll ASF Timer register
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#define ASF_POLL_TIMER_R ( (uint16_t) 0x6c14 )
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// Poll Legacy Timer register
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#define POLL_LEGACY_TIMER_R ( (uint16_t) 0x6c18 )
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// Retransmission Timer register
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#define RETRANSMISSION_TIMER_R ( (uint16_t) 0x6c1c )
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// Time Stamp Counter register
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#define TIME_STAMP_COUNTER_R ( (uint16_t) 0x6c20 )
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// NVM Command register
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#define NVM_COM_R ( (uint16_t) 0x7000 )
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// NVM Write register
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#define NVM_WRITE_R ( (uint16_t) 0x7008 )
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// NVM Address register
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#define NVM_ADDR_R ( (uint16_t) 0x700c )
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// NVM Read registertg3_phy_copper_begin
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#define NVM_READ_R ( (uint16_t) 0x7010 )
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// NVM Access register
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#define NVM_ACC_R ( (uint16_t) 0x7024 )
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// NVM Config 1 register
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#define NVM_CFG1_R ( (uint16_t) 0x7014 )
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// Software arbitration register
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#define SW_ARB_R ( (uint16_t) 0x7020 )
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/*
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* useful def's
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*/
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#define rd08(a) ci_read_8((uint8_t *)(a))
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#define rd16(a) ci_read_16((uint16_t *)(a))
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#define rd32(a) ci_read_32((uint32_t *)(a))
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#define wr08(a,v) ci_write_8((uint8_t *)(a), (v))
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#define wr16(a,v) ci_write_16((uint16_t *)(a), (v))
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#define wr32(a,v) ci_write_32((uint32_t *)(a), (v))
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#define BIT08( bit ) ( (uint8_t) 0x1 << (bit) )
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#define BIT16( bit ) ( (uint16_t) 0x1 << (bit) )
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#define BIT32( bit ) ( (uint32_t) 0x1 << (bit) )
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/*
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* type definition
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*/
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/*
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* Constants for different kinds of IOCTL requests
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*/
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#define SIOCETHTOOL 0x1000
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/*
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* special structure and constants for IOCTL requests of type ETHTOOL
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*/
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#define ETHTOOL_GMAC 0x03
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#define ETHTOOL_SMAC 0x04
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#define ETHTOOL_VERSION 0x05
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typedef struct {
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int idx;
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char address[6];
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} ioctl_ethtool_mac_t;
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typedef struct {
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unsigned int length;
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char *text;
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} ioctl_ethtool_version_t;
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|
/*
|
||
|
|
* default structure and constants for IOCTL requests
|
||
|
|
*/
|
||
|
|
|
||
|
|
#define IF_NAME_SIZE 0xFF
|
||
|
|
|
||
|
|
typedef struct {
|
||
|
|
char if_name[IF_NAME_SIZE];
|
||
|
|
int subcmd;
|
||
|
|
union {
|
||
|
|
ioctl_ethtool_mac_t mac;
|
||
|
|
ioctl_ethtool_version_t version;
|
||
|
|
} data;
|
||
|
|
} ioctl_net_data_t;
|
||
|
|
|
||
|
|
extern net_driver_t *bcm57xx_open(void);
|
||
|
|
extern void bcm57xx_close(net_driver_t *driver);
|
||
|
|
extern int bcm57xx_read(char *buf, int len);
|
||
|
|
extern int bcm57xx_write(char *buf, int len);
|