390 lines
11 KiB
C
390 lines
11 KiB
C
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/** @file
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A PEIM with the following responsibilities:
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- verify & configure the Q35 TSEG in the entry point,
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- provide SMRAM access by producing PEI_SMM_ACCESS_PPI,
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- set aside the SMM_S3_RESUME_STATE object at the bottom of TSEG, and expose
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it via the gEfiAcpiVariableGuid GUID HOB.
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This PEIM runs from RAM, so we can write to variables with static storage
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duration.
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Copyright (C) 2013, 2015, Red Hat, Inc.<BR>
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Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Guid/AcpiS3Context.h>
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#include <Library/BaseLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/DebugLib.h>
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#include <Library/HobLib.h>
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#include <Library/IoLib.h>
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#include <Library/PcdLib.h>
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#include <Library/PciLib.h>
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#include <Library/PeiServicesLib.h>
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#include <Ppi/SmmAccess.h>
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#include <OvmfPlatforms.h>
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#include "SmramInternal.h"
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//
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// PEI_SMM_ACCESS_PPI implementation.
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//
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/**
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Opens the SMRAM area to be accessible by a PEIM driver.
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This function "opens" SMRAM so that it is visible while not inside of SMM.
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The function should return EFI_UNSUPPORTED if the hardware does not support
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hiding of SMRAM. The function should return EFI_DEVICE_ERROR if the SMRAM
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configuration is locked.
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@param PeiServices General purpose services available to every
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PEIM.
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@param This The pointer to the SMM Access Interface.
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@param DescriptorIndex The region of SMRAM to Open.
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@retval EFI_SUCCESS The region was successfully opened.
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@retval EFI_DEVICE_ERROR The region could not be opened because locked
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by chipset.
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@retval EFI_INVALID_PARAMETER The descriptor index was out of bounds.
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**/
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STATIC
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EFI_STATUS
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EFIAPI
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SmmAccessPeiOpen (
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IN EFI_PEI_SERVICES **PeiServices,
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IN PEI_SMM_ACCESS_PPI *This,
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IN UINTN DescriptorIndex
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)
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{
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if (DescriptorIndex >= DescIdxCount) {
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return EFI_INVALID_PARAMETER;
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}
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//
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// According to current practice, DescriptorIndex is not considered at all,
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// beyond validating it.
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//
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return SmramAccessOpen (&This->LockState, &This->OpenState);
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}
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/**
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Inhibits access to the SMRAM.
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This function "closes" SMRAM so that it is not visible while outside of SMM.
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The function should return EFI_UNSUPPORTED if the hardware does not support
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hiding of SMRAM.
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@param PeiServices General purpose services available to every
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PEIM.
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@param This The pointer to the SMM Access Interface.
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@param DescriptorIndex The region of SMRAM to Close.
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@retval EFI_SUCCESS The region was successfully closed.
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@retval EFI_DEVICE_ERROR The region could not be closed because
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locked by chipset.
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@retval EFI_INVALID_PARAMETER The descriptor index was out of bounds.
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**/
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STATIC
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EFI_STATUS
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EFIAPI
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SmmAccessPeiClose (
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IN EFI_PEI_SERVICES **PeiServices,
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IN PEI_SMM_ACCESS_PPI *This,
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IN UINTN DescriptorIndex
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)
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{
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if (DescriptorIndex >= DescIdxCount) {
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return EFI_INVALID_PARAMETER;
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}
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//
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// According to current practice, DescriptorIndex is not considered at all,
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// beyond validating it.
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//
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return SmramAccessClose (&This->LockState, &This->OpenState);
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}
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/**
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Inhibits access to the SMRAM.
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This function prohibits access to the SMRAM region. This function is usually
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implemented such that it is a write-once operation.
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@param PeiServices General purpose services available to every
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PEIM.
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@param This The pointer to the SMM Access Interface.
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@param DescriptorIndex The region of SMRAM to Close.
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@retval EFI_SUCCESS The region was successfully locked.
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@retval EFI_DEVICE_ERROR The region could not be locked because at
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least one range is still open.
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@retval EFI_INVALID_PARAMETER The descriptor index was out of bounds.
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**/
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STATIC
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EFI_STATUS
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EFIAPI
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SmmAccessPeiLock (
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IN EFI_PEI_SERVICES **PeiServices,
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IN PEI_SMM_ACCESS_PPI *This,
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IN UINTN DescriptorIndex
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)
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{
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if (DescriptorIndex >= DescIdxCount) {
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return EFI_INVALID_PARAMETER;
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}
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//
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// According to current practice, DescriptorIndex is not considered at all,
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// beyond validating it.
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//
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return SmramAccessLock (&This->LockState, &This->OpenState);
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}
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/**
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Queries the memory controller for the possible regions that will support
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SMRAM.
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@param PeiServices General purpose services available to every
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PEIM.
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@param This The pointer to the SmmAccessPpi Interface.
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@param SmramMapSize The pointer to the variable containing size of
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the buffer to contain the description
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information.
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@param SmramMap The buffer containing the data describing the
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Smram region descriptors.
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@retval EFI_BUFFER_TOO_SMALL The user did not provide a sufficient buffer.
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@retval EFI_SUCCESS The user provided a sufficiently-sized buffer.
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**/
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STATIC
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EFI_STATUS
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EFIAPI
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SmmAccessPeiGetCapabilities (
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IN EFI_PEI_SERVICES **PeiServices,
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IN PEI_SMM_ACCESS_PPI *This,
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IN OUT UINTN *SmramMapSize,
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IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap
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)
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{
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return SmramAccessGetCapabilities (This->LockState, This->OpenState,
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SmramMapSize, SmramMap);
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}
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//
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// LockState and OpenState will be filled in by the entry point.
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//
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STATIC PEI_SMM_ACCESS_PPI mAccess = {
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&SmmAccessPeiOpen,
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&SmmAccessPeiClose,
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&SmmAccessPeiLock,
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&SmmAccessPeiGetCapabilities
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};
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STATIC EFI_PEI_PPI_DESCRIPTOR mPpiList[] = {
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{
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EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
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&gPeiSmmAccessPpiGuid, &mAccess
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}
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};
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//
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// Utility functions.
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//
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STATIC
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UINT8
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CmosRead8 (
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IN UINT8 Index
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)
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{
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IoWrite8 (0x70, Index);
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return IoRead8 (0x71);
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}
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STATIC
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UINT32
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GetSystemMemorySizeBelow4gb (
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VOID
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)
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{
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UINT32 Cmos0x34;
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UINT32 Cmos0x35;
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Cmos0x34 = CmosRead8 (0x34);
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Cmos0x35 = CmosRead8 (0x35);
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return ((Cmos0x35 << 8 | Cmos0x34) << 16) + SIZE_16MB;
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}
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//
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// Entry point of this driver.
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//
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EFI_STATUS
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EFIAPI
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SmmAccessPeiEntryPoint (
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IN EFI_PEI_FILE_HANDLE FileHandle,
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IN CONST EFI_PEI_SERVICES **PeiServices
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)
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{
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UINT16 HostBridgeDevId;
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UINT8 EsmramcVal;
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UINT8 RegMask8;
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UINT32 TopOfLowRam, TopOfLowRamMb;
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EFI_STATUS Status;
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UINTN SmramMapSize;
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EFI_SMRAM_DESCRIPTOR SmramMap[DescIdxCount];
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VOID *GuidHob;
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//
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// This module should only be included if SMRAM support is required.
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//
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ASSERT (FeaturePcdGet (PcdSmmSmramRequire));
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//
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// Verify if we're running on a Q35 machine type.
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//
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HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
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if (HostBridgeDevId != INTEL_Q35_MCH_DEVICE_ID) {
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DEBUG ((EFI_D_ERROR, "%a: no SMRAM with host bridge DID=0x%04x; only "
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"DID=0x%04x (Q35) is supported\n", __FUNCTION__, HostBridgeDevId,
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INTEL_Q35_MCH_DEVICE_ID));
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goto WrongConfig;
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}
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//
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// Confirm if QEMU supports SMRAM.
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//
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// With no support for it, the ESMRAMC (Extended System Management RAM
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// Control) register reads as zero. If there is support, the cache-enable
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// bits are hard-coded as 1 by QEMU.
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//
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EsmramcVal = PciRead8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC));
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RegMask8 = MCH_ESMRAMC_SM_CACHE | MCH_ESMRAMC_SM_L1 | MCH_ESMRAMC_SM_L2;
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if ((EsmramcVal & RegMask8) != RegMask8) {
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DEBUG ((EFI_D_ERROR, "%a: this Q35 implementation lacks SMRAM\n",
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__FUNCTION__));
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goto WrongConfig;
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}
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TopOfLowRam = GetSystemMemorySizeBelow4gb ();
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ASSERT ((TopOfLowRam & (SIZE_1MB - 1)) == 0);
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TopOfLowRamMb = TopOfLowRam >> 20;
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//
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// Some of the following registers are no-ops for QEMU at the moment, but it
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// is recommended to set them correctly, since the ESMRAMC that we ultimately
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// care about is in the same set of registers.
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//
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// First, we disable the integrated VGA, and set both the GTT Graphics Memory
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// Size and the Graphics Mode Select memory pre-allocation fields to zero.
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// This takes just one write to the Graphics Control Register.
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//
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PciWrite16 (DRAMC_REGISTER_Q35 (MCH_GGC), MCH_GGC_IVD);
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//
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// Set Top of Low Usable DRAM.
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//
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PciWrite16 (DRAMC_REGISTER_Q35 (MCH_TOLUD),
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(UINT16)(TopOfLowRamMb << MCH_TOLUD_MB_SHIFT));
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//
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// Given the zero graphics memory sizes configured above, set the
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// graphics-related stolen memory bases to the same as TOLUD.
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//
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PciWrite32 (DRAMC_REGISTER_Q35 (MCH_GBSM),
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TopOfLowRamMb << MCH_GBSM_MB_SHIFT);
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PciWrite32 (DRAMC_REGISTER_Q35 (MCH_BGSM),
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TopOfLowRamMb << MCH_BGSM_MB_SHIFT);
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//
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// Set TSEG Memory Base.
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//
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InitQ35TsegMbytes ();
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PciWrite32 (DRAMC_REGISTER_Q35 (MCH_TSEGMB),
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(TopOfLowRamMb - mQ35TsegMbytes) << MCH_TSEGMB_MB_SHIFT);
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//
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// Set TSEG size, and disable TSEG visibility outside of SMM. Note that the
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// T_EN bit has inverse meaning; when T_EN is set, then TSEG visibility is
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// *restricted* to SMM.
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//
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EsmramcVal &= ~(UINT32)MCH_ESMRAMC_TSEG_MASK;
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EsmramcVal |= mQ35TsegMbytes == 8 ? MCH_ESMRAMC_TSEG_8MB :
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mQ35TsegMbytes == 2 ? MCH_ESMRAMC_TSEG_2MB :
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mQ35TsegMbytes == 1 ? MCH_ESMRAMC_TSEG_1MB :
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MCH_ESMRAMC_TSEG_EXT;
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EsmramcVal |= MCH_ESMRAMC_T_EN;
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PciWrite8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC), EsmramcVal);
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//
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// TSEG should be closed (see above), but unlocked, initially. Set G_SMRAME
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// (Global SMRAM Enable) too, as both D_LCK and T_EN depend on it.
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//
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PciAndThenOr8 (DRAMC_REGISTER_Q35 (MCH_SMRAM),
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(UINT8)((~(UINT32)MCH_SMRAM_D_LCK) & 0xff), MCH_SMRAM_G_SMRAME);
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//
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// Create the GUID HOB and point it to the first SMRAM range.
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//
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GetStates (&mAccess.LockState, &mAccess.OpenState);
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SmramMapSize = sizeof SmramMap;
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Status = SmramAccessGetCapabilities (mAccess.LockState, mAccess.OpenState,
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&SmramMapSize, SmramMap);
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ASSERT_EFI_ERROR (Status);
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DEBUG_CODE_BEGIN ();
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{
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UINTN Count;
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UINTN Idx;
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Count = SmramMapSize / sizeof SmramMap[0];
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DEBUG ((EFI_D_VERBOSE, "%a: SMRAM map follows, %d entries\n", __FUNCTION__,
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(INT32)Count));
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DEBUG ((EFI_D_VERBOSE, "% 20a % 20a % 20a % 20a\n", "PhysicalStart(0x)",
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"PhysicalSize(0x)", "CpuStart(0x)", "RegionState(0x)"));
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for (Idx = 0; Idx < Count; ++Idx) {
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DEBUG ((EFI_D_VERBOSE, "% 20Lx % 20Lx % 20Lx % 20Lx\n",
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SmramMap[Idx].PhysicalStart, SmramMap[Idx].PhysicalSize,
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SmramMap[Idx].CpuStart, SmramMap[Idx].RegionState));
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}
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}
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DEBUG_CODE_END ();
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GuidHob = BuildGuidHob (&gEfiAcpiVariableGuid,
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sizeof SmramMap[DescIdxSmmS3ResumeState]);
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if (GuidHob == NULL) {
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|
|
return EFI_OUT_OF_RESOURCES;
|
||
|
|
}
|
||
|
|
|
||
|
|
CopyMem (GuidHob, &SmramMap[DescIdxSmmS3ResumeState],
|
||
|
|
sizeof SmramMap[DescIdxSmmS3ResumeState]);
|
||
|
|
|
||
|
|
//
|
||
|
|
// We're done. The next step should succeed, but even if it fails, we can't
|
||
|
|
// roll back the above BuildGuidHob() allocation, because PEI doesn't support
|
||
|
|
// releasing memory.
|
||
|
|
//
|
||
|
|
return PeiServicesInstallPpi (mPpiList);
|
||
|
|
|
||
|
|
WrongConfig:
|
||
|
|
//
|
||
|
|
// We really don't want to continue in this case.
|
||
|
|
//
|
||
|
|
ASSERT (FALSE);
|
||
|
|
CpuDeadLoop ();
|
||
|
|
return EFI_UNSUPPORTED;
|
||
|
|
}
|