61 lines
2.2 KiB
ReStructuredText
61 lines
2.2 KiB
ReStructuredText
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skiboot-5.1.16
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==============
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skiboot-5.1.16 was released on Friday April 29th, 2016.
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skiboot-5.1.16 is the 17th stable release of 5.1, it follows skiboot-5.1.15
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(which was released March 16th, 2016).
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This release contains a few bug fixes and is a recommended upgrade.
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Changes
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-------
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PHB3 (all POWER8 platforms)
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^^^^^^^^^^^^^^^^^^^^^^^^^^^
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- hw/phb3: Ensure PQ bits are cleared in the IVC when masking IRQ
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When we mask an interrupt, we may race with another interrupt coming
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in from the hardware. If this occurs, the P and/or Q bit may end up
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being set but we never EOI/clear them. This could result in a lost
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interrupt or the next interrupt that comes in after re-enabling never
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being presented.
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This fixes a bug seen with some CAPI workloads which have lots of
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interrupt masking at the same time as high interrupt load. The fix is
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not specific to CAPI though.
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- hw/phb3: Fix potential race in EOI
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When we EOI we need to clear the present (P) bit in the Interrupt
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Vector Cache (IVC). We must clear P ensuring that any additional
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interrupts that come in aren't lost while also maintaining coherency
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with the Interrupt Vector Table (IVT).
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To do this, the hardware provides a conditional update bit in the
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IVC. This bit ensures that generation counts between the IVT and the
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IVC updates are synchronised.
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Unfortunately we never set this the bit to conditionally update the P
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bit in the IVC based on the generation count. Also, we didn't set
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what we wanted the new generation count to be if the update was
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successful.
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FSP platforms
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^^^^^^^^^^^^^
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- OPAL:Handle mbox response with bad status:0x24 during FSP termination
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OPAL committed a predictive log with SRC BB822411 in some situations.
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Generic
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^^^^^^^
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- hmi: Fix a bug where partial hmi event was reported to host.
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This bug fix ensures the CPU PIR is reported correctly: ::
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[ 305.628283] Fatal Hypervisor Maintenance interrupt [Not recovered]
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[ 305.628341] Error detail: Malfunction Alert
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[ 305.628388] HMER: 8040000000000000
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- [ 305.628423] CPU PIR: 00000000
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+ [ 200.123021] CPU PIR: 000008e8
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[ 305.628458] [Unit: VSU] Logic core check stop
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