119 lines
4.3 KiB
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119 lines
4.3 KiB
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.. _skiboot-6.0.5:
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=============
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skiboot-6.0.5
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=============
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skiboot 6.0.5 was released on Wednesday July 11th, 2018. It replaces
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:ref:`skiboot-6.0.4` as the current stable release in the 6.0.x series.
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It is recommended that 6.0.5 be used instead of any previous 6.0.x version.
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Over :ref:`skiboot-6.0.4` we have several bug fixes, including important ones
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for NVLINK2 and NX.
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PCI/PHB4
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========
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- phb4: Delay training till after PERST is deasserted
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This helps some cards train on the second PERST (ie fast-reboot). The
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reason is not clear why but it helps, so YOLO!
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- pci: Fix PCI_DEVICE_ID()
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The vendor ID is 16 bits not 8. This error leaves the top of the vendor
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ID in the bottom bits of the device ID, which resulted in e.g. a failure
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to run the PCI quirk for the AST VGA device.
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Fixes: 2b841bf0ef1b (present in v5.7-rc1)
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PHB4/CAPI
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=========
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- phb4/capp: Calculate STQ/DMA read engines based on link-width for PEC
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Presently in CAPI mode the number of STQ/DMA-read engines allocated on
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PEC2 for CAPP is fixed to 6 and 0-30 respectively irrespective of the
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PCI link width. These values are only suitable for x8 cards and
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quickly run out if a x16 card is plugged to a PEC2 attached slot. This
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usually manifests as CAPP reporting TLBI timeout due to these messages
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getting stalled due to insufficient STQs.
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To fix this we update enable_capi_mode() to check if PEC2 chiplet is
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in x16 mode and if yes then we allocate 4/0-47 STQ/DMA-read engines
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for the CAPP traffic.
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- capi: Select the correct IODA table entry for the mbt cache.
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With the current code, the capi mmio window is not correctly configured
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in the IODA table entry. The first entry (generally the non-prefetchable
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BAR) is overwrriten.
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This patch sets the capi window bar at the right place.
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Sensors
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=======
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- occ: sensors: Fix the size of the phandle array 'sensors' in DT
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Fixes: 99505c03f493 (present in v5.10-rc4)
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NPU2/NVLINK2
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============
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- npu2/hw-procedures: Fence bricks via NTL instead of MISC
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There are a couple of places we can set/unset fence for a brick:
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1. MISC register: NPU2_MISC_FENCE_STATE
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2. NTL register for the brick: NPU2_NTL_MISC_CFG1(ndev)
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Recent testing of ATS in combination with GPU reset has exposed a side
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effect of using (1); if fence is set for all six bricks, it triggers a
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sticky nmmu latch which prevents the NPU from getting ATR responses.
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This manifests as a hang in the tests.
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We have npu2_dev_fence_brick() which uses (1), and only two calls to it.
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Replace the call which sets fence with a write to (2). Remove the
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corresponding unset call entirely. It's unneeded because the procedures
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already do a progression from full fence to half to idle using (2).
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- opal/hmi: Display correct chip id while printing NPU FIRs.
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HMIs for NPU xstops are broadcasted to all chips. All cores on all the
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chips receive HMI. HMI handler correctly identifies and extracts the
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NPU FIR details from affected chip, but while printing FIR data it
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prints chip id and location code details of this_cpu()->chip_id which
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may not be correct. This patch fixes this issue.
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Fixes: 7bcbc78c (present in v6.0.1)
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VPD
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===
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- vpd: Add vendor property to processor node
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Processor FRU vpd doesn't contain vendor detail. We have to parse
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module VPD to get vendor detail.
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- vpd: Sanitize VPD data
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On OpenPower system, VPD keyword size tells us the maximum size of the data.
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But they fill trailing end with space (0x20) instead of NULL. Also spec
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doesn't stop user to have space (0x20) within actual data.
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This patch discards trailing spaces before populating device tree.
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NX/VAS for POWER9
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=================
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- NX: Add NX coprocessor init opal call
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The read offset (4:11) in Receive FIFO control register is incremented
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by FIFO size whenever CRB read by NX. But the index in RxFIFO has to
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match with the corresponding entry in FIFO maintained by VAS in kernel.
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VAS entry is reset to 0 when opening the receive window during driver
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initialization. So when NX842 is reloaded or in kexec boot, possibility
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of mismatch between RxFIFO control register and VAS entries in kernel.
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It could cause CRB failure / timeout from NX.
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This patch adds nx_coproc_init opal call for kernel to initialize
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readOffset (4:11) and Queued (15:23) in RxFIFO control register.
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Fixes: 3b3c5962f432 (present in v5.8-rc1)
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