217 lines
7.1 KiB
C
217 lines
7.1 KiB
C
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/*
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* Copyright (C) 2014 - Linaro
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* Author: Rob Herring <rob.herring@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/helper-proto.h"
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#include "kvm-consts.h"
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#include "qemu/main-loop.h"
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#include "sysemu/runstate.h"
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#include "internals.h"
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#include "arm-powerctl.h"
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bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
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{
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/* Return true if the r0/x0 value indicates a PSCI call and
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* the exception type matches the configured PSCI conduit. This is
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* called before the SMC/HVC instruction is executed, to decide whether
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* we should treat it as a PSCI call or with the architecturally
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* defined behaviour for an SMC or HVC (which might be UNDEF or trap
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* to EL2 or to EL3).
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*/
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CPUARMState *env = &cpu->env;
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uint64_t param = is_a64(env) ? env->xregs[0] : env->regs[0];
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switch (excp_type) {
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case EXCP_HVC:
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if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_HVC) {
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return false;
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}
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break;
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case EXCP_SMC:
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if (cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) {
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return false;
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}
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break;
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default:
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return false;
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}
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switch (param) {
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case QEMU_PSCI_0_2_FN_PSCI_VERSION:
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case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
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case QEMU_PSCI_0_2_FN_AFFINITY_INFO:
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case QEMU_PSCI_0_2_FN64_AFFINITY_INFO:
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case QEMU_PSCI_0_2_FN_SYSTEM_RESET:
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case QEMU_PSCI_0_2_FN_SYSTEM_OFF:
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case QEMU_PSCI_0_1_FN_CPU_ON:
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case QEMU_PSCI_0_2_FN_CPU_ON:
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case QEMU_PSCI_0_2_FN64_CPU_ON:
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case QEMU_PSCI_0_1_FN_CPU_OFF:
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case QEMU_PSCI_0_2_FN_CPU_OFF:
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case QEMU_PSCI_0_1_FN_CPU_SUSPEND:
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case QEMU_PSCI_0_2_FN_CPU_SUSPEND:
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case QEMU_PSCI_0_2_FN64_CPU_SUSPEND:
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case QEMU_PSCI_0_1_FN_MIGRATE:
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case QEMU_PSCI_0_2_FN_MIGRATE:
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return true;
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default:
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return false;
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}
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}
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void arm_handle_psci_call(ARMCPU *cpu)
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{
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/*
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* This function partially implements the logic for dispatching Power State
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* Coordination Interface (PSCI) calls (as described in ARM DEN 0022B.b),
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* to the extent required for bringing up and taking down secondary cores,
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* and for handling reset and poweroff requests.
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* Additional information about the calling convention used is available in
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* the document 'SMC Calling Convention' (ARM DEN 0028)
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*/
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CPUARMState *env = &cpu->env;
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uint64_t param[4];
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uint64_t context_id, mpidr;
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target_ulong entry;
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int32_t ret = 0;
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int i;
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for (i = 0; i < 4; i++) {
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/*
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* All PSCI functions take explicit 32-bit or native int sized
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* arguments so we can simply zero-extend all arguments regardless
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* of which exact function we are about to call.
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*/
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param[i] = is_a64(env) ? env->xregs[i] : env->regs[i];
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}
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if ((param[0] & QEMU_PSCI_0_2_64BIT) && !is_a64(env)) {
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ret = QEMU_PSCI_RET_INVALID_PARAMS;
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goto err;
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}
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switch (param[0]) {
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CPUState *target_cpu_state;
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ARMCPU *target_cpu;
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case QEMU_PSCI_0_2_FN_PSCI_VERSION:
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ret = QEMU_PSCI_0_2_RET_VERSION_0_2;
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break;
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case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
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ret = QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED; /* No trusted OS */
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break;
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case QEMU_PSCI_0_2_FN_AFFINITY_INFO:
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case QEMU_PSCI_0_2_FN64_AFFINITY_INFO:
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mpidr = param[1];
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switch (param[2]) {
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case 0:
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target_cpu_state = arm_get_cpu_by_id(mpidr);
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if (!target_cpu_state) {
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ret = QEMU_PSCI_RET_INVALID_PARAMS;
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break;
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}
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target_cpu = ARM_CPU(target_cpu_state);
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g_assert(qemu_mutex_iothread_locked());
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ret = target_cpu->power_state;
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break;
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default:
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/* Everything above affinity level 0 is always on. */
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ret = 0;
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}
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break;
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case QEMU_PSCI_0_2_FN_SYSTEM_RESET:
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qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
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/* QEMU reset and shutdown are async requests, but PSCI
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* mandates that we never return from the reset/shutdown
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* call, so power the CPU off now so it doesn't execute
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* anything further.
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*/
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goto cpu_off;
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case QEMU_PSCI_0_2_FN_SYSTEM_OFF:
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qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
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goto cpu_off;
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case QEMU_PSCI_0_1_FN_CPU_ON:
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case QEMU_PSCI_0_2_FN_CPU_ON:
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case QEMU_PSCI_0_2_FN64_CPU_ON:
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{
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/* The PSCI spec mandates that newly brought up CPUs start
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* in the highest exception level which exists and is enabled
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* on the calling CPU. Since the QEMU PSCI implementation is
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* acting as a "fake EL3" or "fake EL2" firmware, this for us
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* means that we want to start at the highest NS exception level
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* that we are providing to the guest.
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* The execution mode should be that which is currently in use
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* by the same exception level on the calling CPU.
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* The CPU should be started with the context_id value
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* in x0 (if AArch64) or r0 (if AArch32).
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*/
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int target_el = arm_feature(env, ARM_FEATURE_EL2) ? 2 : 1;
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bool target_aarch64 = arm_el_is_aa64(env, target_el);
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mpidr = param[1];
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entry = param[2];
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context_id = param[3];
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ret = arm_set_cpu_on(mpidr, entry, context_id,
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target_el, target_aarch64);
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break;
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}
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case QEMU_PSCI_0_1_FN_CPU_OFF:
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case QEMU_PSCI_0_2_FN_CPU_OFF:
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goto cpu_off;
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case QEMU_PSCI_0_1_FN_CPU_SUSPEND:
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case QEMU_PSCI_0_2_FN_CPU_SUSPEND:
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case QEMU_PSCI_0_2_FN64_CPU_SUSPEND:
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/* Affinity levels are not supported in QEMU */
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if (param[1] & 0xfffe0000) {
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ret = QEMU_PSCI_RET_INVALID_PARAMS;
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break;
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}
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/* Powerdown is not supported, we always go into WFI */
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if (is_a64(env)) {
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env->xregs[0] = 0;
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} else {
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env->regs[0] = 0;
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}
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helper_wfi(env, 4);
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break;
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case QEMU_PSCI_0_1_FN_MIGRATE:
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case QEMU_PSCI_0_2_FN_MIGRATE:
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ret = QEMU_PSCI_RET_NOT_SUPPORTED;
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break;
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default:
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g_assert_not_reached();
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}
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err:
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if (is_a64(env)) {
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env->xregs[0] = ret;
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} else {
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env->regs[0] = ret;
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}
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return;
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cpu_off:
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ret = arm_set_cpu_off(cpu->mp_affinity);
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/* notreached */
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/* sanity check in case something failed */
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assert(ret == QEMU_ARM_POWERCTL_RET_SUCCESS);
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}
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