208 lines
7 KiB
C
208 lines
7 KiB
C
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/*
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* ARM TLB (Translation lookaside buffer) helpers.
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*
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* This code is licensed under the GNU GPL v2 or later.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "internals.h"
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#include "exec/exec-all.h"
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static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
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unsigned int target_el,
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bool same_el, bool ea,
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bool s1ptw, bool is_write,
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int fsc)
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{
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uint32_t syn;
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/*
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* ISV is only set for data aborts routed to EL2 and
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* never for stage-1 page table walks faulting on stage 2.
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*
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* Furthermore, ISV is only set for certain kinds of load/stores.
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* If the template syndrome does not have ISV set, we should leave
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* it cleared.
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*
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* See ARMv8 specs, D7-1974:
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* ISS encoding for an exception from a Data Abort, the
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* ISV field.
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*/
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if (!(template_syn & ARM_EL_ISV) || target_el != 2 || s1ptw) {
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syn = syn_data_abort_no_iss(same_el, 0,
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ea, 0, s1ptw, is_write, fsc);
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} else {
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/*
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* Fields: IL, ISV, SAS, SSE, SRT, SF and AR come from the template
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* syndrome created at translation time.
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* Now we create the runtime syndrome with the remaining fields.
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*/
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syn = syn_data_abort_with_iss(same_el,
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0, 0, 0, 0, 0,
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ea, 0, s1ptw, is_write, fsc,
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true);
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/* Merge the runtime syndrome with the template syndrome. */
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syn |= template_syn;
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}
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return syn;
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}
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static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr,
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MMUAccessType access_type,
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int mmu_idx, ARMMMUFaultInfo *fi)
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{
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CPUARMState *env = &cpu->env;
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int target_el;
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bool same_el;
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uint32_t syn, exc, fsr, fsc;
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ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx);
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target_el = exception_target_el(env);
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if (fi->stage2) {
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target_el = 2;
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env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4;
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}
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same_el = (arm_current_el(env) == target_el);
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if (target_el == 2 || arm_el_is_aa64(env, target_el) ||
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arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) {
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/*
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* LPAE format fault status register : bottom 6 bits are
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* status code in the same form as needed for syndrome
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*/
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fsr = arm_fi_to_lfsc(fi);
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fsc = extract32(fsr, 0, 6);
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} else {
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fsr = arm_fi_to_sfsc(fi);
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/*
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* Short format FSR : this fault will never actually be reported
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* to an EL that uses a syndrome register. Use a (currently)
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* reserved FSR code in case the constructed syndrome does leak
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* into the guest somehow.
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*/
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fsc = 0x3f;
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}
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if (access_type == MMU_INST_FETCH) {
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syn = syn_insn_abort(same_el, fi->ea, fi->s1ptw, fsc);
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exc = EXCP_PREFETCH_ABORT;
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} else {
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syn = merge_syn_data_abort(env->exception.syndrome, target_el,
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same_el, fi->ea, fi->s1ptw,
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access_type == MMU_DATA_STORE,
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fsc);
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if (access_type == MMU_DATA_STORE
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&& arm_feature(env, ARM_FEATURE_V6)) {
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fsr |= (1 << 11);
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}
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exc = EXCP_DATA_ABORT;
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}
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env->exception.vaddress = addr;
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env->exception.fsr = fsr;
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raise_exception(env, exc, syn, target_el);
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}
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/* Raise a data fault alignment exception for the specified virtual address */
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void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
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MMUAccessType access_type,
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int mmu_idx, uintptr_t retaddr)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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ARMMMUFaultInfo fi = {};
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/* now we have a real cpu fault */
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cpu_restore_state(cs, retaddr, true);
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fi.type = ARMFault_Alignment;
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arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi);
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}
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#if !defined(CONFIG_USER_ONLY)
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/*
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* arm_cpu_do_transaction_failed: handle a memory system error response
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* (eg "no device/memory present at address") by raising an external abort
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* exception
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*/
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void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
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vaddr addr, unsigned size,
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MMUAccessType access_type,
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int mmu_idx, MemTxAttrs attrs,
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MemTxResult response, uintptr_t retaddr)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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ARMMMUFaultInfo fi = {};
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/* now we have a real cpu fault */
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cpu_restore_state(cs, retaddr, true);
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fi.ea = arm_extabort_type(response);
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fi.type = ARMFault_SyncExternal;
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arm_deliver_fault(cpu, addr, access_type, mmu_idx, &fi);
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}
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#endif /* !defined(CONFIG_USER_ONLY) */
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bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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#ifdef CONFIG_USER_ONLY
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cpu->env.exception.vaddress = address;
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if (access_type == MMU_INST_FETCH) {
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cs->exception_index = EXCP_PREFETCH_ABORT;
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} else {
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cs->exception_index = EXCP_DATA_ABORT;
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}
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cpu_loop_exit_restore(cs, retaddr);
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#else
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hwaddr phys_addr;
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target_ulong page_size;
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int prot, ret;
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MemTxAttrs attrs = {};
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ARMMMUFaultInfo fi = {};
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ARMCacheAttrs cacheattrs = {};
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/*
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* Walk the page table and (if the mapping exists) add the page
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* to the TLB. On success, return true. Otherwise, if probing,
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* return false. Otherwise populate fsr with ARM DFSR/IFSR fault
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* register format, and signal the fault.
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*/
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ret = get_phys_addr(&cpu->env, address, access_type,
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core_to_arm_mmu_idx(&cpu->env, mmu_idx),
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&phys_addr, &attrs, &prot, &page_size,
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&fi, &cacheattrs);
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if (likely(!ret)) {
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/*
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* Map a single [sub]page. Regions smaller than our declared
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* target page size are handled specially, so for those we
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* pass in the exact addresses.
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*/
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if (page_size >= TARGET_PAGE_SIZE) {
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phys_addr &= TARGET_PAGE_MASK;
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address &= TARGET_PAGE_MASK;
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}
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/* Notice and record tagged memory. */
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if (cpu_isar_feature(aa64_mte, cpu) && cacheattrs.attrs == 0xf0) {
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arm_tlb_mte_tagged(&attrs) = true;
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}
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tlb_set_page_with_attrs(cs, address, phys_addr, attrs,
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prot, mmu_idx, page_size);
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return true;
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} else if (probe) {
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return false;
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} else {
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/* now we have a real cpu fault */
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cpu_restore_state(cs, retaddr, true);
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arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi);
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}
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#endif
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}
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