324 lines
9.4 KiB
C
324 lines
9.4 KiB
C
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/*
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* Copyright (C) 2016 Veertu Inc,
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* Copyright (C) 2017 Veertu Inc,
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HVF_X86_H
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#define HVF_X86_H
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typedef struct x86_register {
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union {
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struct {
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uint64_t rrx; /* full 64 bit */
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};
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struct {
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uint32_t erx; /* low 32 bit part */
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uint32_t hi32_unused1;
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};
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struct {
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uint16_t rx; /* low 16 bit part */
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uint16_t hi16_unused1;
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uint32_t hi32_unused2;
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};
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struct {
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uint8_t lx; /* low 8 bit part */
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uint8_t hx; /* high 8 bit */
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uint16_t hi16_unused2;
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uint32_t hi32_unused3;
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};
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};
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} __attribute__ ((__packed__)) x86_register;
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typedef enum x86_reg_cr0 {
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CR0_PE = (1L << 0),
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CR0_MP = (1L << 1),
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CR0_EM = (1L << 2),
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CR0_TS = (1L << 3),
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CR0_ET = (1L << 4),
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CR0_NE = (1L << 5),
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CR0_WP = (1L << 16),
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CR0_AM = (1L << 18),
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CR0_NW = (1L << 29),
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CR0_CD = (1L << 30),
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CR0_PG = (1L << 31),
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} x86_reg_cr0;
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typedef enum x86_reg_cr4 {
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CR4_VME = (1L << 0),
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CR4_PVI = (1L << 1),
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CR4_TSD = (1L << 2),
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CR4_DE = (1L << 3),
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CR4_PSE = (1L << 4),
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CR4_PAE = (1L << 5),
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CR4_MSE = (1L << 6),
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CR4_PGE = (1L << 7),
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CR4_PCE = (1L << 8),
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CR4_OSFXSR = (1L << 9),
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CR4_OSXMMEXCPT = (1L << 10),
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CR4_VMXE = (1L << 13),
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CR4_SMXE = (1L << 14),
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CR4_FSGSBASE = (1L << 16),
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CR4_PCIDE = (1L << 17),
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CR4_OSXSAVE = (1L << 18),
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CR4_SMEP = (1L << 20),
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} x86_reg_cr4;
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/* 16 bit Task State Segment */
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typedef struct x86_tss_segment16 {
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uint16_t link;
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uint16_t sp0;
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uint16_t ss0;
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uint32_t sp1;
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uint16_t ss1;
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uint32_t sp2;
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uint16_t ss2;
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uint16_t ip;
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uint16_t flags;
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uint16_t ax;
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uint16_t cx;
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uint16_t dx;
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uint16_t bx;
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uint16_t sp;
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uint16_t bp;
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uint16_t si;
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uint16_t di;
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uint16_t es;
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uint16_t cs;
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uint16_t ss;
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uint16_t ds;
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uint16_t ldtr;
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} __attribute__((packed)) x86_tss_segment16;
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/* 32 bit Task State Segment */
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typedef struct x86_tss_segment32 {
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uint32_t prev_tss;
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uint32_t esp0;
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uint32_t ss0;
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uint32_t esp1;
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uint32_t ss1;
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uint32_t esp2;
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uint32_t ss2;
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uint32_t cr3;
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uint32_t eip;
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uint32_t eflags;
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uint32_t eax;
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uint32_t ecx;
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uint32_t edx;
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uint32_t ebx;
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uint32_t esp;
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uint32_t ebp;
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uint32_t esi;
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uint32_t edi;
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uint32_t es;
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uint32_t cs;
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uint32_t ss;
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uint32_t ds;
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uint32_t fs;
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uint32_t gs;
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uint32_t ldt;
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uint16_t trap;
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uint16_t iomap_base;
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} __attribute__ ((__packed__)) x86_tss_segment32;
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/* 64 bit Task State Segment */
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typedef struct x86_tss_segment64 {
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uint32_t unused;
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uint64_t rsp0;
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uint64_t rsp1;
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uint64_t rsp2;
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uint64_t unused1;
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uint64_t ist1;
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uint64_t ist2;
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uint64_t ist3;
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uint64_t ist4;
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uint64_t ist5;
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uint64_t ist6;
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uint64_t ist7;
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uint64_t unused2;
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uint16_t unused3;
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uint16_t iomap_base;
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} __attribute__ ((__packed__)) x86_tss_segment64;
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/* segment descriptors */
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typedef struct x86_segment_descriptor {
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uint64_t limit0:16;
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uint64_t base0:16;
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uint64_t base1:8;
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uint64_t type:4;
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uint64_t s:1;
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uint64_t dpl:2;
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uint64_t p:1;
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uint64_t limit1:4;
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uint64_t avl:1;
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uint64_t l:1;
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uint64_t db:1;
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uint64_t g:1;
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uint64_t base2:8;
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} __attribute__ ((__packed__)) x86_segment_descriptor;
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static inline uint32_t x86_segment_base(x86_segment_descriptor *desc)
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{
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return (uint32_t)((desc->base2 << 24) | (desc->base1 << 16) | desc->base0);
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}
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static inline void x86_set_segment_base(x86_segment_descriptor *desc,
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uint32_t base)
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{
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desc->base2 = base >> 24;
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desc->base1 = (base >> 16) & 0xff;
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desc->base0 = base & 0xffff;
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}
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static inline uint32_t x86_segment_limit(x86_segment_descriptor *desc)
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{
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uint32_t limit = (uint32_t)((desc->limit1 << 16) | desc->limit0);
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if (desc->g) {
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return (limit << 12) | 0xfff;
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}
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return limit;
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}
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static inline void x86_set_segment_limit(x86_segment_descriptor *desc,
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uint32_t limit)
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{
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desc->limit0 = limit & 0xffff;
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desc->limit1 = limit >> 16;
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}
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typedef struct x86_call_gate {
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uint64_t offset0:16;
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uint64_t selector:16;
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uint64_t param_count:4;
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uint64_t reserved:3;
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uint64_t type:4;
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uint64_t dpl:1;
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uint64_t p:1;
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uint64_t offset1:16;
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} __attribute__ ((__packed__)) x86_call_gate;
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static inline uint32_t x86_call_gate_offset(x86_call_gate *gate)
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{
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return (uint32_t)((gate->offset1 << 16) | gate->offset0);
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}
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#define LDT_SEL 0
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#define GDT_SEL 1
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typedef struct x68_segment_selector {
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union {
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uint16_t sel;
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struct {
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uint16_t rpl:3;
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uint16_t ti:1;
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uint16_t index:12;
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};
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};
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} __attribute__ ((__packed__)) x68_segment_selector;
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/* useful register access macros */
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#define x86_reg(cpu, reg) ((x86_register *) &cpu->regs[reg])
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#define RRX(cpu, reg) (x86_reg(cpu, reg)->rrx)
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#define RAX(cpu) RRX(cpu, R_EAX)
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#define RCX(cpu) RRX(cpu, R_ECX)
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#define RDX(cpu) RRX(cpu, R_EDX)
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#define RBX(cpu) RRX(cpu, R_EBX)
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#define RSP(cpu) RRX(cpu, R_ESP)
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#define RBP(cpu) RRX(cpu, R_EBP)
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#define RSI(cpu) RRX(cpu, R_ESI)
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#define RDI(cpu) RRX(cpu, R_EDI)
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#define R8(cpu) RRX(cpu, R_R8)
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#define R9(cpu) RRX(cpu, R_R9)
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#define R10(cpu) RRX(cpu, R_R10)
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#define R11(cpu) RRX(cpu, R_R11)
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#define R12(cpu) RRX(cpu, R_R12)
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#define R13(cpu) RRX(cpu, R_R13)
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#define R14(cpu) RRX(cpu, R_R14)
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#define R15(cpu) RRX(cpu, R_R15)
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#define ERX(cpu, reg) (x86_reg(cpu, reg)->erx)
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#define EAX(cpu) ERX(cpu, R_EAX)
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#define ECX(cpu) ERX(cpu, R_ECX)
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#define EDX(cpu) ERX(cpu, R_EDX)
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#define EBX(cpu) ERX(cpu, R_EBX)
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#define ESP(cpu) ERX(cpu, R_ESP)
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#define EBP(cpu) ERX(cpu, R_EBP)
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#define ESI(cpu) ERX(cpu, R_ESI)
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#define EDI(cpu) ERX(cpu, R_EDI)
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#define RX(cpu, reg) (x86_reg(cpu, reg)->rx)
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#define AX(cpu) RX(cpu, R_EAX)
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#define CX(cpu) RX(cpu, R_ECX)
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#define DX(cpu) RX(cpu, R_EDX)
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#define BP(cpu) RX(cpu, R_EBP)
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#define SP(cpu) RX(cpu, R_ESP)
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#define BX(cpu) RX(cpu, R_EBX)
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#define SI(cpu) RX(cpu, R_ESI)
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#define DI(cpu) RX(cpu, R_EDI)
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#define RL(cpu, reg) (x86_reg(cpu, reg)->lx)
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#define AL(cpu) RL(cpu, R_EAX)
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#define CL(cpu) RL(cpu, R_ECX)
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#define DL(cpu) RL(cpu, R_EDX)
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#define BL(cpu) RL(cpu, R_EBX)
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#define RH(cpu, reg) (x86_reg(cpu, reg)->hx)
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#define AH(cpu) RH(cpu, R_EAX)
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#define CH(cpu) RH(cpu, R_ECX)
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#define DH(cpu) RH(cpu, R_EDX)
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#define BH(cpu) RH(cpu, R_EBX)
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/* deal with GDT/LDT descriptors in memory */
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bool x86_read_segment_descriptor(struct CPUState *cpu,
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struct x86_segment_descriptor *desc,
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x68_segment_selector sel);
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bool x86_write_segment_descriptor(struct CPUState *cpu,
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struct x86_segment_descriptor *desc,
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x68_segment_selector sel);
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bool x86_read_call_gate(struct CPUState *cpu, struct x86_call_gate *idt_desc,
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int gate);
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/* helpers */
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bool x86_is_protected(struct CPUState *cpu);
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bool x86_is_real(struct CPUState *cpu);
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bool x86_is_v8086(struct CPUState *cpu);
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bool x86_is_long_mode(struct CPUState *cpu);
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bool x86_is_long64_mode(struct CPUState *cpu);
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bool x86_is_paging_mode(struct CPUState *cpu);
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bool x86_is_pae_enabled(struct CPUState *cpu);
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enum X86Seg;
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target_ulong linear_addr(struct CPUState *cpu, target_ulong addr, enum X86Seg seg);
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target_ulong linear_addr_size(struct CPUState *cpu, target_ulong addr, int size,
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enum X86Seg seg);
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target_ulong linear_rip(struct CPUState *cpu, target_ulong rip);
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static inline uint64_t rdtscp(void)
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{
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uint64_t tsc;
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__asm__ __volatile__("rdtscp; " /* serializing read of tsc */
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"shl $32,%%rdx; " /* shift higher 32 bits stored in rdx up */
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"or %%rdx,%%rax" /* and or onto rax */
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: "=a"(tsc) /* output to tsc variable */
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:
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: "%rcx", "%rdx"); /* rcx and rdx are clobbered */
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return tsc;
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}
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#endif
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