186 lines
6.3 KiB
C
186 lines
6.3 KiB
C
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// This software is licensed under the terms of the GNU General Public
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// License version 2, as published by the Free Software Foundation, and
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// may be copied, distributed, and modified under those terms.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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#include "qemu/osdep.h"
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#include "panic.h"
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#include "qemu-common.h"
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#include "qemu/error-report.h"
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#include "sysemu/hvf.h"
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#include "hvf-i386.h"
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#include "vmcs.h"
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#include "vmx.h"
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#include "x86.h"
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#include "x86_descr.h"
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#include "x86_mmu.h"
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#include "x86_decode.h"
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#include "x86_emu.h"
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#include "x86_task.h"
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#include "x86hvf.h"
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#include <Hypervisor/hv.h>
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#include <Hypervisor/hv_vmx.h>
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#include "hw/i386/apic_internal.h"
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#include "qemu/main-loop.h"
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#include "sysemu/accel.h"
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#include "target/i386/cpu.h"
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// TODO: taskswitch handling
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static void save_state_to_tss32(CPUState *cpu, struct x86_tss_segment32 *tss)
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{
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X86CPU *x86_cpu = X86_CPU(cpu);
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CPUX86State *env = &x86_cpu->env;
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/* CR3 and ldt selector are not saved intentionally */
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tss->eip = (uint32_t)env->eip;
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tss->eflags = (uint32_t)env->eflags;
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tss->eax = EAX(env);
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tss->ecx = ECX(env);
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tss->edx = EDX(env);
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tss->ebx = EBX(env);
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tss->esp = ESP(env);
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tss->ebp = EBP(env);
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tss->esi = ESI(env);
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tss->edi = EDI(env);
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tss->es = vmx_read_segment_selector(cpu, R_ES).sel;
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tss->cs = vmx_read_segment_selector(cpu, R_CS).sel;
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tss->ss = vmx_read_segment_selector(cpu, R_SS).sel;
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tss->ds = vmx_read_segment_selector(cpu, R_DS).sel;
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tss->fs = vmx_read_segment_selector(cpu, R_FS).sel;
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tss->gs = vmx_read_segment_selector(cpu, R_GS).sel;
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}
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static void load_state_from_tss32(CPUState *cpu, struct x86_tss_segment32 *tss)
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{
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X86CPU *x86_cpu = X86_CPU(cpu);
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CPUX86State *env = &x86_cpu->env;
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wvmcs(cpu->hvf_fd, VMCS_GUEST_CR3, tss->cr3);
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env->eip = tss->eip;
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env->eflags = tss->eflags | 2;
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/* General purpose registers */
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RAX(env) = tss->eax;
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RCX(env) = tss->ecx;
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RDX(env) = tss->edx;
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RBX(env) = tss->ebx;
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RSP(env) = tss->esp;
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RBP(env) = tss->ebp;
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RSI(env) = tss->esi;
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RDI(env) = tss->edi;
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vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ldt}}, R_LDTR);
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vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->es}}, R_ES);
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vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->cs}}, R_CS);
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vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ss}}, R_SS);
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vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ds}}, R_DS);
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vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->fs}}, R_FS);
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vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->gs}}, R_GS);
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}
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static int task_switch_32(CPUState *cpu, x68_segment_selector tss_sel, x68_segment_selector old_tss_sel,
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uint64_t old_tss_base, struct x86_segment_descriptor *new_desc)
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{
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struct x86_tss_segment32 tss_seg;
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uint32_t new_tss_base = x86_segment_base(new_desc);
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uint32_t eip_offset = offsetof(struct x86_tss_segment32, eip);
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uint32_t ldt_sel_offset = offsetof(struct x86_tss_segment32, ldt);
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vmx_read_mem(cpu, &tss_seg, old_tss_base, sizeof(tss_seg));
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save_state_to_tss32(cpu, &tss_seg);
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vmx_write_mem(cpu, old_tss_base + eip_offset, &tss_seg.eip, ldt_sel_offset - eip_offset);
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vmx_read_mem(cpu, &tss_seg, new_tss_base, sizeof(tss_seg));
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if (old_tss_sel.sel != 0xffff) {
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tss_seg.prev_tss = old_tss_sel.sel;
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vmx_write_mem(cpu, new_tss_base, &tss_seg.prev_tss, sizeof(tss_seg.prev_tss));
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}
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load_state_from_tss32(cpu, &tss_seg);
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return 0;
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}
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void vmx_handle_task_switch(CPUState *cpu, x68_segment_selector tss_sel, int reason, bool gate_valid, uint8_t gate, uint64_t gate_type)
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{
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uint64_t rip = rreg(cpu->hvf_fd, HV_X86_RIP);
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if (!gate_valid || (gate_type != VMCS_INTR_T_HWEXCEPTION &&
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gate_type != VMCS_INTR_T_HWINTR &&
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gate_type != VMCS_INTR_T_NMI)) {
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int ins_len = rvmcs(cpu->hvf_fd, VMCS_EXIT_INSTRUCTION_LENGTH);
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macvm_set_rip(cpu, rip + ins_len);
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return;
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}
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load_regs(cpu);
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struct x86_segment_descriptor curr_tss_desc, next_tss_desc;
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int ret;
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x68_segment_selector old_tss_sel = vmx_read_segment_selector(cpu, R_TR);
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uint64_t old_tss_base = vmx_read_segment_base(cpu, R_TR);
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uint32_t desc_limit;
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struct x86_call_gate task_gate_desc;
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struct vmx_segment vmx_seg;
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X86CPU *x86_cpu = X86_CPU(cpu);
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CPUX86State *env = &x86_cpu->env;
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x86_read_segment_descriptor(cpu, &next_tss_desc, tss_sel);
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x86_read_segment_descriptor(cpu, &curr_tss_desc, old_tss_sel);
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if (reason == TSR_IDT_GATE && gate_valid) {
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int dpl;
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ret = x86_read_call_gate(cpu, &task_gate_desc, gate);
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dpl = task_gate_desc.dpl;
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x68_segment_selector cs = vmx_read_segment_selector(cpu, R_CS);
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if (tss_sel.rpl > dpl || cs.rpl > dpl)
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;//DPRINTF("emulate_gp");
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}
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desc_limit = x86_segment_limit(&next_tss_desc);
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if (!next_tss_desc.p || ((desc_limit < 0x67 && (next_tss_desc.type & 8)) || desc_limit < 0x2b)) {
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VM_PANIC("emulate_ts");
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}
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if (reason == TSR_IRET || reason == TSR_JMP) {
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curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
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x86_write_segment_descriptor(cpu, &curr_tss_desc, old_tss_sel);
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}
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if (reason == TSR_IRET)
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env->eflags &= ~NT_MASK;
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if (reason != TSR_CALL && reason != TSR_IDT_GATE)
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old_tss_sel.sel = 0xffff;
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if (reason != TSR_IRET) {
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next_tss_desc.type |= (1 << 1); /* set busy flag */
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x86_write_segment_descriptor(cpu, &next_tss_desc, tss_sel);
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}
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if (next_tss_desc.type & 8)
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ret = task_switch_32(cpu, tss_sel, old_tss_sel, old_tss_base, &next_tss_desc);
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else
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//ret = task_switch_16(cpu, tss_sel, old_tss_sel, old_tss_base, &next_tss_desc);
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VM_PANIC("task_switch_16");
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macvm_set_cr0(cpu->hvf_fd, rvmcs(cpu->hvf_fd, VMCS_GUEST_CR0) | CR0_TS);
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x86_segment_descriptor_to_vmx(cpu, tss_sel, &next_tss_desc, &vmx_seg);
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vmx_write_segment_descriptor(cpu, &vmx_seg, R_TR);
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store_regs(cpu);
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hv_vcpu_invalidate_tlb(cpu->hvf_fd);
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hv_vcpu_flush(cpu->hvf_fd);
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}
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