333 lines
13 KiB
C
333 lines
13 KiB
C
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/*
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* x86 SMM helpers
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/main-loop.h"
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#include "cpu.h"
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#include "exec/helper-proto.h"
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#include "exec/log.h"
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/* SMM support */
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#if defined(CONFIG_USER_ONLY)
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void do_smm_enter(X86CPU *cpu)
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{
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}
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void helper_rsm(CPUX86State *env)
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{
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}
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#else
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#ifdef TARGET_X86_64
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#define SMM_REVISION_ID 0x00020064
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#else
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#define SMM_REVISION_ID 0x00020000
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#endif
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void do_smm_enter(X86CPU *cpu)
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{
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CPUX86State *env = &cpu->env;
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CPUState *cs = CPU(cpu);
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target_ulong sm_state;
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SegmentCache *dt;
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int i, offset;
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qemu_log_mask(CPU_LOG_INT, "SMM: enter\n");
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log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP);
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env->msr_smi_count++;
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env->hflags |= HF_SMM_MASK;
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if (env->hflags2 & HF2_NMI_MASK) {
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env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
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} else {
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env->hflags2 |= HF2_NMI_MASK;
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}
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sm_state = env->smbase + 0x8000;
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#ifdef TARGET_X86_64
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for (i = 0; i < 6; i++) {
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dt = &env->segs[i];
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offset = 0x7e00 + i * 16;
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x86_stw_phys(cs, sm_state + offset, dt->selector);
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x86_stw_phys(cs, sm_state + offset + 2, (dt->flags >> 8) & 0xf0ff);
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x86_stl_phys(cs, sm_state + offset + 4, dt->limit);
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x86_stq_phys(cs, sm_state + offset + 8, dt->base);
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}
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x86_stq_phys(cs, sm_state + 0x7e68, env->gdt.base);
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x86_stl_phys(cs, sm_state + 0x7e64, env->gdt.limit);
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x86_stw_phys(cs, sm_state + 0x7e70, env->ldt.selector);
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x86_stq_phys(cs, sm_state + 0x7e78, env->ldt.base);
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x86_stl_phys(cs, sm_state + 0x7e74, env->ldt.limit);
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x86_stw_phys(cs, sm_state + 0x7e72, (env->ldt.flags >> 8) & 0xf0ff);
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x86_stq_phys(cs, sm_state + 0x7e88, env->idt.base);
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x86_stl_phys(cs, sm_state + 0x7e84, env->idt.limit);
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x86_stw_phys(cs, sm_state + 0x7e90, env->tr.selector);
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x86_stq_phys(cs, sm_state + 0x7e98, env->tr.base);
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x86_stl_phys(cs, sm_state + 0x7e94, env->tr.limit);
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x86_stw_phys(cs, sm_state + 0x7e92, (env->tr.flags >> 8) & 0xf0ff);
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/* ??? Vol 1, 16.5.6 Intel MPX and SMM says that IA32_BNDCFGS
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is saved at offset 7ED0. Vol 3, 34.4.1.1, Table 32-2, has
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7EA0-7ED7 as "reserved". What's this, and what's really
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supposed to happen? */
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x86_stq_phys(cs, sm_state + 0x7ed0, env->efer);
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x86_stq_phys(cs, sm_state + 0x7ff8, env->regs[R_EAX]);
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x86_stq_phys(cs, sm_state + 0x7ff0, env->regs[R_ECX]);
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x86_stq_phys(cs, sm_state + 0x7fe8, env->regs[R_EDX]);
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x86_stq_phys(cs, sm_state + 0x7fe0, env->regs[R_EBX]);
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x86_stq_phys(cs, sm_state + 0x7fd8, env->regs[R_ESP]);
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x86_stq_phys(cs, sm_state + 0x7fd0, env->regs[R_EBP]);
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x86_stq_phys(cs, sm_state + 0x7fc8, env->regs[R_ESI]);
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x86_stq_phys(cs, sm_state + 0x7fc0, env->regs[R_EDI]);
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for (i = 8; i < 16; i++) {
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x86_stq_phys(cs, sm_state + 0x7ff8 - i * 8, env->regs[i]);
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}
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x86_stq_phys(cs, sm_state + 0x7f78, env->eip);
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x86_stl_phys(cs, sm_state + 0x7f70, cpu_compute_eflags(env));
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x86_stl_phys(cs, sm_state + 0x7f68, env->dr[6]);
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x86_stl_phys(cs, sm_state + 0x7f60, env->dr[7]);
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x86_stl_phys(cs, sm_state + 0x7f48, env->cr[4]);
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x86_stq_phys(cs, sm_state + 0x7f50, env->cr[3]);
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x86_stl_phys(cs, sm_state + 0x7f58, env->cr[0]);
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x86_stl_phys(cs, sm_state + 0x7efc, SMM_REVISION_ID);
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x86_stl_phys(cs, sm_state + 0x7f00, env->smbase);
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#else
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x86_stl_phys(cs, sm_state + 0x7ffc, env->cr[0]);
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x86_stl_phys(cs, sm_state + 0x7ff8, env->cr[3]);
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x86_stl_phys(cs, sm_state + 0x7ff4, cpu_compute_eflags(env));
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x86_stl_phys(cs, sm_state + 0x7ff0, env->eip);
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x86_stl_phys(cs, sm_state + 0x7fec, env->regs[R_EDI]);
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x86_stl_phys(cs, sm_state + 0x7fe8, env->regs[R_ESI]);
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x86_stl_phys(cs, sm_state + 0x7fe4, env->regs[R_EBP]);
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x86_stl_phys(cs, sm_state + 0x7fe0, env->regs[R_ESP]);
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x86_stl_phys(cs, sm_state + 0x7fdc, env->regs[R_EBX]);
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x86_stl_phys(cs, sm_state + 0x7fd8, env->regs[R_EDX]);
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x86_stl_phys(cs, sm_state + 0x7fd4, env->regs[R_ECX]);
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x86_stl_phys(cs, sm_state + 0x7fd0, env->regs[R_EAX]);
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x86_stl_phys(cs, sm_state + 0x7fcc, env->dr[6]);
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x86_stl_phys(cs, sm_state + 0x7fc8, env->dr[7]);
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x86_stl_phys(cs, sm_state + 0x7fc4, env->tr.selector);
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x86_stl_phys(cs, sm_state + 0x7f64, env->tr.base);
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x86_stl_phys(cs, sm_state + 0x7f60, env->tr.limit);
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x86_stl_phys(cs, sm_state + 0x7f5c, (env->tr.flags >> 8) & 0xf0ff);
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x86_stl_phys(cs, sm_state + 0x7fc0, env->ldt.selector);
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x86_stl_phys(cs, sm_state + 0x7f80, env->ldt.base);
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x86_stl_phys(cs, sm_state + 0x7f7c, env->ldt.limit);
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x86_stl_phys(cs, sm_state + 0x7f78, (env->ldt.flags >> 8) & 0xf0ff);
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x86_stl_phys(cs, sm_state + 0x7f74, env->gdt.base);
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x86_stl_phys(cs, sm_state + 0x7f70, env->gdt.limit);
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x86_stl_phys(cs, sm_state + 0x7f58, env->idt.base);
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x86_stl_phys(cs, sm_state + 0x7f54, env->idt.limit);
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for (i = 0; i < 6; i++) {
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dt = &env->segs[i];
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if (i < 3) {
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offset = 0x7f84 + i * 12;
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} else {
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offset = 0x7f2c + (i - 3) * 12;
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}
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x86_stl_phys(cs, sm_state + 0x7fa8 + i * 4, dt->selector);
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x86_stl_phys(cs, sm_state + offset + 8, dt->base);
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x86_stl_phys(cs, sm_state + offset + 4, dt->limit);
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x86_stl_phys(cs, sm_state + offset, (dt->flags >> 8) & 0xf0ff);
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}
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x86_stl_phys(cs, sm_state + 0x7f14, env->cr[4]);
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x86_stl_phys(cs, sm_state + 0x7efc, SMM_REVISION_ID);
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x86_stl_phys(cs, sm_state + 0x7ef8, env->smbase);
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#endif
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/* init SMM cpu state */
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#ifdef TARGET_X86_64
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cpu_load_efer(env, 0);
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#endif
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cpu_load_eflags(env, 0, ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C |
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DF_MASK));
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env->eip = 0x00008000;
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cpu_x86_update_cr0(env,
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env->cr[0] & ~(CR0_PE_MASK | CR0_EM_MASK | CR0_TS_MASK |
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CR0_PG_MASK));
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cpu_x86_update_cr4(env, 0);
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env->dr[7] = 0x00000400;
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cpu_x86_load_seg_cache(env, R_CS, (env->smbase >> 4) & 0xffff, env->smbase,
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0xffffffff,
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DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
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DESC_G_MASK | DESC_A_MASK);
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cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffffffff,
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DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
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DESC_G_MASK | DESC_A_MASK);
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cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffffffff,
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DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
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DESC_G_MASK | DESC_A_MASK);
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cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffffffff,
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DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
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DESC_G_MASK | DESC_A_MASK);
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cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffffffff,
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DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
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DESC_G_MASK | DESC_A_MASK);
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cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffffffff,
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DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
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DESC_G_MASK | DESC_A_MASK);
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}
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void helper_rsm(CPUX86State *env)
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{
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X86CPU *cpu = env_archcpu(env);
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CPUState *cs = env_cpu(env);
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target_ulong sm_state;
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int i, offset;
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uint32_t val;
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sm_state = env->smbase + 0x8000;
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#ifdef TARGET_X86_64
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cpu_load_efer(env, x86_ldq_phys(cs, sm_state + 0x7ed0));
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env->gdt.base = x86_ldq_phys(cs, sm_state + 0x7e68);
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env->gdt.limit = x86_ldl_phys(cs, sm_state + 0x7e64);
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env->ldt.selector = x86_lduw_phys(cs, sm_state + 0x7e70);
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env->ldt.base = x86_ldq_phys(cs, sm_state + 0x7e78);
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env->ldt.limit = x86_ldl_phys(cs, sm_state + 0x7e74);
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env->ldt.flags = (x86_lduw_phys(cs, sm_state + 0x7e72) & 0xf0ff) << 8;
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env->idt.base = x86_ldq_phys(cs, sm_state + 0x7e88);
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env->idt.limit = x86_ldl_phys(cs, sm_state + 0x7e84);
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env->tr.selector = x86_lduw_phys(cs, sm_state + 0x7e90);
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env->tr.base = x86_ldq_phys(cs, sm_state + 0x7e98);
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env->tr.limit = x86_ldl_phys(cs, sm_state + 0x7e94);
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env->tr.flags = (x86_lduw_phys(cs, sm_state + 0x7e92) & 0xf0ff) << 8;
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env->regs[R_EAX] = x86_ldq_phys(cs, sm_state + 0x7ff8);
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env->regs[R_ECX] = x86_ldq_phys(cs, sm_state + 0x7ff0);
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env->regs[R_EDX] = x86_ldq_phys(cs, sm_state + 0x7fe8);
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env->regs[R_EBX] = x86_ldq_phys(cs, sm_state + 0x7fe0);
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env->regs[R_ESP] = x86_ldq_phys(cs, sm_state + 0x7fd8);
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env->regs[R_EBP] = x86_ldq_phys(cs, sm_state + 0x7fd0);
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env->regs[R_ESI] = x86_ldq_phys(cs, sm_state + 0x7fc8);
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env->regs[R_EDI] = x86_ldq_phys(cs, sm_state + 0x7fc0);
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for (i = 8; i < 16; i++) {
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env->regs[i] = x86_ldq_phys(cs, sm_state + 0x7ff8 - i * 8);
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}
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env->eip = x86_ldq_phys(cs, sm_state + 0x7f78);
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cpu_load_eflags(env, x86_ldl_phys(cs, sm_state + 0x7f70),
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~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
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env->dr[6] = x86_ldl_phys(cs, sm_state + 0x7f68);
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env->dr[7] = x86_ldl_phys(cs, sm_state + 0x7f60);
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cpu_x86_update_cr4(env, x86_ldl_phys(cs, sm_state + 0x7f48));
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cpu_x86_update_cr3(env, x86_ldq_phys(cs, sm_state + 0x7f50));
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cpu_x86_update_cr0(env, x86_ldl_phys(cs, sm_state + 0x7f58));
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for (i = 0; i < 6; i++) {
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offset = 0x7e00 + i * 16;
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cpu_x86_load_seg_cache(env, i,
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x86_lduw_phys(cs, sm_state + offset),
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x86_ldq_phys(cs, sm_state + offset + 8),
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x86_ldl_phys(cs, sm_state + offset + 4),
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(x86_lduw_phys(cs, sm_state + offset + 2) &
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0xf0ff) << 8);
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}
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val = x86_ldl_phys(cs, sm_state + 0x7efc); /* revision ID */
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if (val & 0x20000) {
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env->smbase = x86_ldl_phys(cs, sm_state + 0x7f00);
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}
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#else
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cpu_x86_update_cr0(env, x86_ldl_phys(cs, sm_state + 0x7ffc));
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cpu_x86_update_cr3(env, x86_ldl_phys(cs, sm_state + 0x7ff8));
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cpu_load_eflags(env, x86_ldl_phys(cs, sm_state + 0x7ff4),
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~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
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env->eip = x86_ldl_phys(cs, sm_state + 0x7ff0);
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env->regs[R_EDI] = x86_ldl_phys(cs, sm_state + 0x7fec);
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||
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|
env->regs[R_ESI] = x86_ldl_phys(cs, sm_state + 0x7fe8);
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||
|
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env->regs[R_EBP] = x86_ldl_phys(cs, sm_state + 0x7fe4);
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||
|
|
env->regs[R_ESP] = x86_ldl_phys(cs, sm_state + 0x7fe0);
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||
|
|
env->regs[R_EBX] = x86_ldl_phys(cs, sm_state + 0x7fdc);
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||
|
|
env->regs[R_EDX] = x86_ldl_phys(cs, sm_state + 0x7fd8);
|
||
|
|
env->regs[R_ECX] = x86_ldl_phys(cs, sm_state + 0x7fd4);
|
||
|
|
env->regs[R_EAX] = x86_ldl_phys(cs, sm_state + 0x7fd0);
|
||
|
|
env->dr[6] = x86_ldl_phys(cs, sm_state + 0x7fcc);
|
||
|
|
env->dr[7] = x86_ldl_phys(cs, sm_state + 0x7fc8);
|
||
|
|
|
||
|
|
env->tr.selector = x86_ldl_phys(cs, sm_state + 0x7fc4) & 0xffff;
|
||
|
|
env->tr.base = x86_ldl_phys(cs, sm_state + 0x7f64);
|
||
|
|
env->tr.limit = x86_ldl_phys(cs, sm_state + 0x7f60);
|
||
|
|
env->tr.flags = (x86_ldl_phys(cs, sm_state + 0x7f5c) & 0xf0ff) << 8;
|
||
|
|
|
||
|
|
env->ldt.selector = x86_ldl_phys(cs, sm_state + 0x7fc0) & 0xffff;
|
||
|
|
env->ldt.base = x86_ldl_phys(cs, sm_state + 0x7f80);
|
||
|
|
env->ldt.limit = x86_ldl_phys(cs, sm_state + 0x7f7c);
|
||
|
|
env->ldt.flags = (x86_ldl_phys(cs, sm_state + 0x7f78) & 0xf0ff) << 8;
|
||
|
|
|
||
|
|
env->gdt.base = x86_ldl_phys(cs, sm_state + 0x7f74);
|
||
|
|
env->gdt.limit = x86_ldl_phys(cs, sm_state + 0x7f70);
|
||
|
|
|
||
|
|
env->idt.base = x86_ldl_phys(cs, sm_state + 0x7f58);
|
||
|
|
env->idt.limit = x86_ldl_phys(cs, sm_state + 0x7f54);
|
||
|
|
|
||
|
|
for (i = 0; i < 6; i++) {
|
||
|
|
if (i < 3) {
|
||
|
|
offset = 0x7f84 + i * 12;
|
||
|
|
} else {
|
||
|
|
offset = 0x7f2c + (i - 3) * 12;
|
||
|
|
}
|
||
|
|
cpu_x86_load_seg_cache(env, i,
|
||
|
|
x86_ldl_phys(cs,
|
||
|
|
sm_state + 0x7fa8 + i * 4) & 0xffff,
|
||
|
|
x86_ldl_phys(cs, sm_state + offset + 8),
|
||
|
|
x86_ldl_phys(cs, sm_state + offset + 4),
|
||
|
|
(x86_ldl_phys(cs,
|
||
|
|
sm_state + offset) & 0xf0ff) << 8);
|
||
|
|
}
|
||
|
|
cpu_x86_update_cr4(env, x86_ldl_phys(cs, sm_state + 0x7f14));
|
||
|
|
|
||
|
|
val = x86_ldl_phys(cs, sm_state + 0x7efc); /* revision ID */
|
||
|
|
if (val & 0x20000) {
|
||
|
|
env->smbase = x86_ldl_phys(cs, sm_state + 0x7ef8);
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
if ((env->hflags2 & HF2_SMM_INSIDE_NMI_MASK) == 0) {
|
||
|
|
env->hflags2 &= ~HF2_NMI_MASK;
|
||
|
|
}
|
||
|
|
env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
|
||
|
|
env->hflags &= ~HF_SMM_MASK;
|
||
|
|
|
||
|
|
qemu_log_mask(CPU_LOG_INT, "SMM: after RSM\n");
|
||
|
|
log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP);
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif /* !CONFIG_USER_ONLY */
|