121 lines
3.1 KiB
C
121 lines
3.1 KiB
C
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/*
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* RISC-V translation routines for the RV64M Standard Extension.
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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* Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
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* Bastian Koppelmann, kbastian@mail.uni-paderborn.de
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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static bool trans_mul(DisasContext *ctx, arg_mul *a)
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{
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REQUIRE_EXT(ctx, RVM);
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return gen_arith(ctx, a, &tcg_gen_mul_tl);
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}
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static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
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{
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REQUIRE_EXT(ctx, RVM);
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TCGv source1 = tcg_temp_new();
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TCGv source2 = tcg_temp_new();
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gen_get_gpr(source1, a->rs1);
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gen_get_gpr(source2, a->rs2);
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tcg_gen_muls2_tl(source2, source1, source1, source2);
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gen_set_gpr(a->rd, source1);
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tcg_temp_free(source1);
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tcg_temp_free(source2);
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return true;
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}
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static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
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{
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REQUIRE_EXT(ctx, RVM);
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return gen_arith(ctx, a, &gen_mulhsu);
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}
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static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
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{
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REQUIRE_EXT(ctx, RVM);
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TCGv source1 = tcg_temp_new();
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TCGv source2 = tcg_temp_new();
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gen_get_gpr(source1, a->rs1);
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gen_get_gpr(source2, a->rs2);
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tcg_gen_mulu2_tl(source2, source1, source1, source2);
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gen_set_gpr(a->rd, source1);
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tcg_temp_free(source1);
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tcg_temp_free(source2);
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return true;
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}
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static bool trans_div(DisasContext *ctx, arg_div *a)
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{
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REQUIRE_EXT(ctx, RVM);
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return gen_arith(ctx, a, &gen_div);
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}
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static bool trans_divu(DisasContext *ctx, arg_divu *a)
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{
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REQUIRE_EXT(ctx, RVM);
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return gen_arith(ctx, a, &gen_divu);
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}
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static bool trans_rem(DisasContext *ctx, arg_rem *a)
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{
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REQUIRE_EXT(ctx, RVM);
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return gen_arith(ctx, a, &gen_rem);
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}
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static bool trans_remu(DisasContext *ctx, arg_remu *a)
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{
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REQUIRE_EXT(ctx, RVM);
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return gen_arith(ctx, a, &gen_remu);
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}
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#ifdef TARGET_RISCV64
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static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
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{
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REQUIRE_EXT(ctx, RVM);
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return gen_arith(ctx, a, &gen_mulw);
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}
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static bool trans_divw(DisasContext *ctx, arg_divw *a)
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{
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REQUIRE_EXT(ctx, RVM);
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return gen_arith_div_w(ctx, a, &gen_div);
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}
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static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
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{
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REQUIRE_EXT(ctx, RVM);
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return gen_arith_div_uw(ctx, a, &gen_divu);
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}
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static bool trans_remw(DisasContext *ctx, arg_remw *a)
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{
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REQUIRE_EXT(ctx, RVM);
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return gen_arith_div_w(ctx, a, &gen_rem);
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}
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static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
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{
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REQUIRE_EXT(ctx, RVM);
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return gen_arith_div_uw(ctx, a, &gen_remu);
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}
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#endif
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