87 lines
3 KiB
C
87 lines
3 KiB
C
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/*
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*
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* Copyright (c) 2019 Jonathan Afek <jonyafek@me.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu-common.h"
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#include "hw/arm/boot.h"
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#include "sysemu/sysemu.h"
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#include "qemu/error-report.h"
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#include "hw/arm/xnu_cpacr.h"
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#include "hw/loader.h"
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static CpacrIntCtx ctx = {0};
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static void cpacr_a32_s_int_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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ctx.wfn_a32_s(env, ri, ctx.val);
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}
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static void cpacr_a32_s_int_reset(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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cpacr_a32_s_int_write(env, ri, ctx.val);
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}
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static void cpacr_a32_ns_int_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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ctx.wfn_a32_ns(env, ri, ctx.val);
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}
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static void cpacr_a32_ns_int_reset(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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cpacr_a32_ns_int_write(env, ri, ctx.val);
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}
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static void cpacr_a64_intercept_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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ctx.wfn_a64(env, ri, ctx.val);
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}
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static void cpacr_a64_intercept_reset(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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cpacr_a64_intercept_write(env, ri, ctx.val);
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}
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void xnu_cpacr_intercept_write_const_val(ARMCPU *cpu, uint64_t val)
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{
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ctx.val = val;
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uint32_t key = ENCODE_AA64_CP_REG(19, 1, 0, 3, 0, 2);
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ARMCPRegInfo *ri = (ARMCPRegInfo *)get_arm_cp_reginfo(cpu->cp_regs, key);
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ctx.wfn_a64 = ri->writefn;
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ri->writefn = cpacr_a64_intercept_write;
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ri->resetfn = cpacr_a64_intercept_reset;
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key = ENCODE_CP_REG(15, 0, 1, 1, 0, 0, 2);
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ri = (ARMCPRegInfo *)get_arm_cp_reginfo(cpu->cp_regs, key);
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ctx.wfn_a32_ns = ri->writefn;
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ri->writefn = cpacr_a32_ns_int_write;
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ri->resetfn = cpacr_a32_ns_int_reset;
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key = ENCODE_CP_REG(15, 0, 0, 1, 0, 0, 2);
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ri = (ARMCPRegInfo *)get_arm_cp_reginfo(cpu->cp_regs, key);
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ctx.wfn_a32_s = ri->writefn;
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ri->writefn = cpacr_a32_s_int_write;
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ri->resetfn = cpacr_a32_s_int_reset;
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}
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