308 lines
6.3 KiB
C
308 lines
6.3 KiB
C
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/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*/
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_encoding.h>
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#include <sbi/sbi_error.h>
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#include <sbi/sbi_platform.h>
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/* determine CPU extension, return non-zero support */
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int misa_extension_imp(char ext)
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{
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unsigned long misa = csr_read(CSR_MISA);
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if (misa)
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return misa & (1 << (ext - 'A'));
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return sbi_platform_misa_extension(sbi_platform_thishart_ptr(), ext);
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}
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int misa_xlen(void)
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{
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long r;
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if (csr_read(CSR_MISA) == 0)
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return sbi_platform_misa_xlen(sbi_platform_thishart_ptr());
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__asm__ __volatile__(
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"csrr t0, misa\n\t"
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"slti t1, t0, 0\n\t"
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"slli t1, t1, 1\n\t"
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"slli t0, t0, 1\n\t"
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"slti t0, t0, 0\n\t"
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"add %0, t0, t1"
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: "=r"(r)
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:
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: "t0", "t1");
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return r ? r : -1;
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}
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unsigned long csr_read_num(int csr_num)
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{
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unsigned long ret = 0;
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switch (csr_num) {
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case CSR_PMPCFG0:
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ret = csr_read(CSR_PMPCFG0);
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break;
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case CSR_PMPCFG1:
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ret = csr_read(CSR_PMPCFG1);
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break;
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case CSR_PMPCFG2:
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ret = csr_read(CSR_PMPCFG2);
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break;
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case CSR_PMPCFG3:
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ret = csr_read(CSR_PMPCFG3);
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break;
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case CSR_PMPADDR0:
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ret = csr_read(CSR_PMPADDR0);
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break;
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case CSR_PMPADDR1:
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ret = csr_read(CSR_PMPADDR1);
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break;
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case CSR_PMPADDR2:
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ret = csr_read(CSR_PMPADDR2);
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break;
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case CSR_PMPADDR3:
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ret = csr_read(CSR_PMPADDR3);
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break;
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case CSR_PMPADDR4:
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ret = csr_read(CSR_PMPADDR4);
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break;
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case CSR_PMPADDR5:
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ret = csr_read(CSR_PMPADDR5);
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break;
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case CSR_PMPADDR6:
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ret = csr_read(CSR_PMPADDR6);
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break;
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case CSR_PMPADDR7:
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ret = csr_read(CSR_PMPADDR7);
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break;
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case CSR_PMPADDR8:
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ret = csr_read(CSR_PMPADDR8);
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break;
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case CSR_PMPADDR9:
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ret = csr_read(CSR_PMPADDR9);
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break;
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case CSR_PMPADDR10:
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ret = csr_read(CSR_PMPADDR10);
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break;
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case CSR_PMPADDR11:
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ret = csr_read(CSR_PMPADDR11);
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break;
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case CSR_PMPADDR12:
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ret = csr_read(CSR_PMPADDR12);
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break;
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case CSR_PMPADDR13:
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ret = csr_read(CSR_PMPADDR13);
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break;
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case CSR_PMPADDR14:
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ret = csr_read(CSR_PMPADDR14);
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break;
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case CSR_PMPADDR15:
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ret = csr_read(CSR_PMPADDR15);
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break;
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default:
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break;
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};
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return ret;
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}
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void csr_write_num(int csr_num, unsigned long val)
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{
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switch (csr_num) {
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case CSR_PMPCFG0:
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csr_write(CSR_PMPCFG0, val);
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break;
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case CSR_PMPCFG1:
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csr_write(CSR_PMPCFG1, val);
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break;
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case CSR_PMPCFG2:
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csr_write(CSR_PMPCFG2, val);
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break;
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case CSR_PMPCFG3:
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csr_write(CSR_PMPCFG3, val);
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break;
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case CSR_PMPADDR0:
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csr_write(CSR_PMPADDR0, val);
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break;
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case CSR_PMPADDR1:
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csr_write(CSR_PMPADDR1, val);
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break;
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case CSR_PMPADDR2:
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csr_write(CSR_PMPADDR2, val);
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break;
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case CSR_PMPADDR3:
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csr_write(CSR_PMPADDR3, val);
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break;
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case CSR_PMPADDR4:
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csr_write(CSR_PMPADDR4, val);
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break;
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case CSR_PMPADDR5:
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csr_write(CSR_PMPADDR5, val);
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break;
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case CSR_PMPADDR6:
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csr_write(CSR_PMPADDR6, val);
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break;
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case CSR_PMPADDR7:
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csr_write(CSR_PMPADDR7, val);
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break;
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case CSR_PMPADDR8:
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csr_write(CSR_PMPADDR8, val);
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break;
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case CSR_PMPADDR9:
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csr_write(CSR_PMPADDR9, val);
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break;
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case CSR_PMPADDR10:
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csr_write(CSR_PMPADDR10, val);
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break;
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case CSR_PMPADDR11:
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csr_write(CSR_PMPADDR11, val);
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break;
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case CSR_PMPADDR12:
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csr_write(CSR_PMPADDR12, val);
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break;
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case CSR_PMPADDR13:
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csr_write(CSR_PMPADDR13, val);
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break;
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case CSR_PMPADDR14:
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csr_write(CSR_PMPADDR14, val);
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break;
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case CSR_PMPADDR15:
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csr_write(CSR_PMPADDR15, val);
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break;
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default:
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break;
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};
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}
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static unsigned long ctz(unsigned long x)
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{
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unsigned long ret = 0;
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while (!(x & 1UL)) {
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ret++;
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x = x >> 1;
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}
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return ret;
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}
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int pmp_set(unsigned int n, unsigned long prot, unsigned long addr,
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unsigned long log2len)
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{
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int pmpcfg_csr, pmpcfg_shift, pmpaddr_csr;
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unsigned long cfgmask, pmpcfg;
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unsigned long addrmask, pmpaddr;
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/* check parameters */
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if (n >= PMP_COUNT || log2len > __riscv_xlen || log2len < PMP_SHIFT)
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return SBI_EINVAL;
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/* calculate PMP register and offset */
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#if __riscv_xlen == 32
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pmpcfg_csr = CSR_PMPCFG0 + (n >> 2);
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pmpcfg_shift = (n & 3) << 3;
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#elif __riscv_xlen == 64
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pmpcfg_csr = (CSR_PMPCFG0 + (n >> 2)) & ~1;
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pmpcfg_shift = (n & 7) << 3;
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#else
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pmpcfg_csr = -1;
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pmpcfg_shift = -1;
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#endif
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pmpaddr_csr = CSR_PMPADDR0 + n;
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if (pmpcfg_csr < 0 || pmpcfg_shift < 0)
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return SBI_ENOTSUPP;
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/* encode PMP config */
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prot |= (log2len == PMP_SHIFT) ? PMP_A_NA4 : PMP_A_NAPOT;
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cfgmask = ~(0xff << pmpcfg_shift);
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pmpcfg = (csr_read_num(pmpcfg_csr) & cfgmask);
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pmpcfg |= ((prot << pmpcfg_shift) & ~cfgmask);
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/* encode PMP address */
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if (log2len == PMP_SHIFT) {
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pmpaddr = (addr >> PMP_SHIFT);
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} else {
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if (log2len == __riscv_xlen) {
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pmpaddr = -1UL;
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} else {
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addrmask = (1UL << (log2len - PMP_SHIFT)) - 1;
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pmpaddr = ((addr >> PMP_SHIFT) & ~addrmask);
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pmpaddr |= (addrmask >> 1);
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}
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}
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/* write csrs */
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csr_write_num(pmpaddr_csr, pmpaddr);
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csr_write_num(pmpcfg_csr, pmpcfg);
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return 0;
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}
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int pmp_get(unsigned int n, unsigned long *prot_out, unsigned long *addr_out,
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unsigned long *size)
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{
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int pmpcfg_csr, pmpcfg_shift, pmpaddr_csr;
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unsigned long cfgmask, pmpcfg, prot;
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unsigned long t1, addr, log2len;
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/* check parameters */
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if (n >= PMP_COUNT || !prot_out || !addr_out || !size)
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return SBI_EINVAL;
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*prot_out = *addr_out = *size = 0;
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/* calculate PMP register and offset */
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#if __riscv_xlen == 32
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pmpcfg_csr = CSR_PMPCFG0 + (n >> 2);
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pmpcfg_shift = (n & 3) << 3;
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#elif __riscv_xlen == 64
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pmpcfg_csr = (CSR_PMPCFG0 + (n >> 2)) & ~1;
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pmpcfg_shift = (n & 7) << 3;
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#else
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pmpcfg_csr = -1;
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pmpcfg_shift = -1;
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#endif
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pmpaddr_csr = CSR_PMPADDR0 + n;
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if (pmpcfg_csr < 0 || pmpcfg_shift < 0)
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return SBI_ENOTSUPP;
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/* decode PMP config */
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cfgmask = (0xff << pmpcfg_shift);
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pmpcfg = csr_read_num(pmpcfg_csr) & cfgmask;
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prot = pmpcfg >> pmpcfg_shift;
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/* decode PMP address */
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if ((prot & PMP_A) == PMP_A_NAPOT) {
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addr = csr_read_num(pmpaddr_csr);
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if (addr == -1UL) {
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addr = 0;
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log2len = __riscv_xlen;
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} else {
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t1 = ctz(~addr);
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addr = (addr & ~((1UL << t1) - 1)) << PMP_SHIFT;
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log2len = (t1 + PMP_SHIFT + 1);
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}
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} else {
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addr = csr_read_num(pmpaddr_csr) << PMP_SHIFT;
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log2len = PMP_SHIFT;
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}
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/* return details */
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*prot_out = prot;
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*addr_out = addr;
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if (log2len < __riscv_xlen)
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*size = (1UL << log2len);
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return 0;
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}
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