794 lines
20 KiB
Tcl
794 lines
20 KiB
Tcl
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#
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# behave like gdb
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#
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set target_t 0
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set target_c 0
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set target_p 0
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proc target { { t 0 } { c 0 } { p 0 } } {
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global target_t
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global target_c
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global target_p
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set target_t $t
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set target_c $c
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set target_p $p
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return "targeting cpu $p:$c:$t"
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}
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proc p { reg { t -1 } { c -1 } { p -1 } } {
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global target_t
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global target_c
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global target_p
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if { $t == -1 } { set t $target_t }
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if { $c == -1 } { set c $target_c }
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if { $p == -1 } { set p $target_p }
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switch -regexp $reg {
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^r$ {
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set val [mysim cpu $p:$c:$t display gprs]
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}
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^r[0-9]+$ {
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regexp "r(\[0-9\]*)" $reg dummy num
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set val [mysim cpu $p:$c:$t display gpr $num]
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}
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^f[0-9]+$ {
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regexp "f(\[0-9\]*)" $reg dummy num
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set val [mysim cpu $p:$c:$t display fpr $num]
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}
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^v[0-9]+$ {
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regexp "v(\[0-9\]*)" $reg dummy num
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set val [mysim cpu $p:$c:$t display vmxr $num]
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}
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default {
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set val [mysim cpu $p:$c:$t display spr $reg]
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}
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}
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return "$val"
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}
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#
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# behave like gdb
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#
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proc sr { reg val { t -1} { c -1 } { p -1 } } {
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global target_t
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global target_c
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global target_p
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if { $t == -1 } { set t $target_t }
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if { $c == -1 } { set c $target_c }
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if { $p == -1 } { set p $target_p }
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switch -regexp $reg {
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^r[0-9]+$ {
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regexp "r(\[0-9\]*)" $reg dummy num
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mysim cpu $p:$c:$t set gpr $num $val
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}
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^f[0-9]+$ {
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regexp "f(\[0-9\]*)" $reg dummy num
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mysim cpu $p:$c:$t set fpr $num $val
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}
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^v[0-9]+$ {
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regexp "v(\[0-9\]*)" $reg dummy num
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mysim cpu $p:$c:$t set vmxr $num $val
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}
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default {
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mysim cpu $p:$c:$t set spr $reg $val
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}
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}
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p $reg $t
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}
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proc b { addr } {
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mysim trigger set pc $addr "just_stop"
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set at [i $addr]
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puts "breakpoint set at $at"
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}
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# Run until $console_string appears on the Linux console
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#
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# eg.
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# break_on_console "Freeing unused kernel memory:"
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# break_on_console "buildroot login:"
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proc break_on_console { console_string } {
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mysim trigger set console "$console_string" "just_stop"
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}
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proc clear_console_break { console_string } {
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mysim trigger clear console "$console_string"
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}
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proc wr { start stop } {
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mysim trigger set memory system w $start $stop 0 "just_stop"
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}
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proc c { } {
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mysim go
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}
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proc i { pc { t -1 } { c -1 } { p -1 } } {
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global target_t
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global target_c
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global target_p
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if { $t == -1 } { set t $target_t }
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if { $c == -1 } { set c $target_c }
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if { $p == -1 } { set p $target_p }
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set pc_laddr [mysim cpu $p:$c:$t util itranslate $pc]
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set inst [mysim cpu $p:$c:$t memory display $pc_laddr 4]
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set disasm [mysim cpu $p:$c:$t util ppc_disasm $inst $pc]
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return "\[$p:$c:$t\]: $pc ($pc_laddr) Enc:$inst : $disasm"
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}
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proc ipc { { t -1 } { c -1 } { p -1 } } {
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global target_t
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global target_c
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global target_p
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if { $t == -1 } { set t $target_t }
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if { $c == -1 } { set c $target_c }
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if { $p == -1 } { set p $target_p }
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set pc [mysim cpu $p:$c:$t display spr pc]
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i $pc $t $c $p
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}
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proc ipca { } {
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set cpus [myconf query cpus]
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set threads [myconf query processor/number_of_threads]
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for { set i 0 } { $i < $cpus } { incr i 1 } {
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for { set j 0 } { $j < $threads } { incr j 1 } {
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puts [ipc $j $i]
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}
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}
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}
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proc pa { spr } {
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set cpus [myconf query cpus]
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set threads [myconf query processor/number_of_threads]
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for { set i 0 } { $i < $cpus } { incr i 1 } {
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for { set j 0 } { $j < $threads } { incr j 1 } {
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set val [mysim cpu $i thread $j display spr $spr]
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puts "CPU: $i THREAD: $j SPR $spr = $val"
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}
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}
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}
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proc s { {nr 1} } {
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for { set i 0 } { $i < $nr } { incr i 1 } {
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mysim step 1
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ipca
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}
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}
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proc S { {nr 1} } {
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upvar #0 target_t t
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upvar #0 target_c c
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upvar #0 target_p p
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for { set i 0 } { $i < $nr } { incr i 1 } {
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mysim cpu $p:$c:$t step 1
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puts [ipc]
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}
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}
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proc z { count } {
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while { $count > 0 } {
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s
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incr count -1
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}
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}
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proc sample_pc { sample count } {
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while { $count > 0 } {
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mysim cycle $sample
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ipc
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incr count -1
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}
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}
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proc e2p { ea } {
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upvar #0 target_t t
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upvar #0 target_c c
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upvar #0 target_p p
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set pa [ mysim cpu $p:$c:$t util dtranslate $ea ]
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puts "$pa"
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}
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proc x { pa { size 8 } } {
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set val [ mysim memory display $pa $size ]
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puts "$pa : $val"
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}
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proc it { ea } {
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upvar #0 target_t t
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upvar #0 target_c c
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upvar #0 target_p p
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mysim cpu $p:$c:$t util itranslate $ea
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}
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proc dt { ea } {
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upvar #0 target_t t
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upvar #0 target_c c
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upvar #0 target_p p
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mysim cpu $p:$c:$t util dtranslate $ea
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}
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proc ex { ea { size 8 } } {
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upvar #0 target_t t
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upvar #0 target_c c
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upvar #0 target_p p
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set pa [ mysim cpu $p:$c:$t util dtranslate $ea ]
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set val [ mysim memory display $pa $size ]
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puts "$pa : $val"
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}
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proc di { location { count 16 } } {
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set addr [expr $location & 0xfffffffffffffff0]
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disasm_mem mysim $addr $count
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}
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proc hexdump { location count } {
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set addr [expr $location & 0xfffffffffffffff0]
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set top [expr $addr + ($count * 15)]
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for { set i $addr } { $i < $top } { incr i 16 } {
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set val [expr $i + (4 * 0)]
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set val0 [format "%08x" [mysim memory display $val 4]]
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set val [expr $i + (4 * 1)]
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set val1 [format "%08x" [mysim memory display $val 4]]
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set val [expr $i + (4 * 2)]
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set val2 [format "%08x" [mysim memory display $val 4]]
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set val [expr $i + (4 * 3)]
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set val3 [format "%08x" [mysim memory display $val 4]]
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set ascii ""
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for { set j 0 } { $j < 16 } { incr j } {
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set byte [get_char [expr $i + $j]]
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if { $byte < 0x20 || $byte >= 127} {
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set c "."
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} else {
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set c [format %c $byte]
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}
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set ascii [string cat "$ascii" "$c"]
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}
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set loc [format "0x%016x" $i]
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puts "$loc: $val0 $val1 $val2 $val3 $ascii"
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}
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}
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proc get_char { addr } {
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return [expr [mysim memory display "$addr" 1]]
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}
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proc p_str { addr { limit 0 } } {
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set addr_limit 0xfffffffffffffffff
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if { $limit > 0 } { set addr_limit [expr $limit + $addr] }
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set s ""
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for {} { [get_char "$addr"] != 0} { incr addr 1 } {
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# memory display returns hex values with a leading 0x
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set c [format %c [get_char "$addr"]]
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set s [string cat "$s" "$c"]
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if { $addr == $addr_limit } { break }
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}
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puts "$s"
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}
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proc slbv {} {
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upvar #0 target_t t
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upvar #0 target_c c
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upvar #0 target_p p
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puts [mysim cpu $p:$c:$t display slb valid]
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}
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proc regs { { t -1 } { c -1 } { p -1 }} {
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global target_t
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global target_c
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global target_p
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if { $t == -1 } { set t $target_t }
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if { $c == -1 } { set c $target_c }
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if { $p == -1 } { set p $target_p }
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puts "GPRS:"
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puts [mysim cpu $p:$c:$t display gprs]
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}
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proc tlbv {} {
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upvar #0 target_t t
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upvar #0 target_c c
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upvar #0 target_p p
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puts "$p:$c:$t:TLB: ----------------------"
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puts [mysim cpu $p:$c:$t display tlb valid]
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}
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proc exc { { i SystemReset } } {
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upvar #0 target_t t
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upvar #0 target_c c
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upvar #0 target_p p
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puts "$p:$c:$t:EXCEPTION:$i"
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puts [mysim cpu $p:$c:$t interrupt $i]
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}
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proc just_stop { args } {
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simstop
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ipca
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}
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proc st { count } {
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upvar #0 target_t t
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upvar #0 target_c c
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upvar #0 target_p p
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set sp [mysim cpu $p:$c:$t display gpr 1]
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puts "SP: $sp"
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ipc
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set lr [mysim cpu $p:$c:$t display spr lr]
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i $lr
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while { $count > 0 } {
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set sp [mysim cpu $p:$c:$t util itranslate $sp]
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set lr [mysim memory display [expr $sp++16] 8]
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i $lr
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set sp [mysim memory display $sp 8]
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incr count -1
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}
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}
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proc mywatch { } {
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while { [mysim memory display 0x700 8] != 0 } {
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mysim cycle 1
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}
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puts "condition occurred "
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ipc
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}
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#
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# force gdb to attach
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#
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proc gdb { { timeout 0 } } {
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mysim set fast off
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mysim debugger wait $timeout
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}
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proc egdb { { timeout 0 }} {
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upvar #0 target_t t
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upvar #0 target_c c
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upvar #0 target_p p
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set srr0 [mysim cpu $p:$c:$t display spr srr0]
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set srr1 [mysim cpu $p:$c:$t display spr srr1]
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mysim cpu $p:$c:$t set spr pc $srr0
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mysim cpu $p:$c:$t set spr msr $srr1
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gdb $timeout
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}
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proc mem_display_64_le { addr } {
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set data 0
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for {set i 0} {$i < 8} {incr i} {
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set data [ expr $data << 8 ]
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set l [ mysim memory display [ expr $addr+7-$i ] 1 ]
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set data [ expr $data | $l ]
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}
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return [format 0x%X $data]
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}
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proc mem_display_64 { addr le } {
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|
|
if { $le } {
|
||
|
|
return [ mem_display_64_le $addr ]
|
||
|
|
}
|
||
|
|
# mysim memory display is big endian
|
||
|
|
return [ mysim memory display $addr 8 ]
|
||
|
|
}
|
||
|
|
|
||
|
|
proc bt { {sp 0} } {
|
||
|
|
upvar #0 target_t t
|
||
|
|
upvar #0 target_c c
|
||
|
|
upvar #0 target_p p
|
||
|
|
|
||
|
|
set lr [mysim cpu $p:$c:$t display spr pc]
|
||
|
|
set sym [addr2func $lr]
|
||
|
|
puts "pc:\t\t\t\t$lr\t$sym"
|
||
|
|
if { $sp == 0 } {
|
||
|
|
set sp [mysim cpu $p:$c:$t display gpr 1]
|
||
|
|
}
|
||
|
|
set lr [mysim cpu $p:$c:$t display spr lr]
|
||
|
|
set sym [addr2func $lr]
|
||
|
|
puts "lr:\t\t\t\t$lr\t$sym"
|
||
|
|
|
||
|
|
set msr [mysim cpu $p:$c:$t display spr msr]
|
||
|
|
set le [ expr $msr & 1 ]
|
||
|
|
|
||
|
|
# Limit to 200 in case of an infinite loop
|
||
|
|
for {set i 0} {$i < 200} {incr i} {
|
||
|
|
set pa [ mysim cpu $p:$c:$t util dtranslate $sp ]
|
||
|
|
set bc [ mem_display_64 $pa $le ]
|
||
|
|
set lr [ mem_display_64 [ expr $pa + 16 ] $le ]
|
||
|
|
set sym [addr2func $lr]
|
||
|
|
puts "stack:$pa \t$lr\t$sym"
|
||
|
|
if { $bc == 0 } { break }
|
||
|
|
set sp $bc
|
||
|
|
}
|
||
|
|
puts ""
|
||
|
|
}
|
||
|
|
|
||
|
|
proc ton { } {mysim mode turbo }
|
||
|
|
proc toff { } {mysim mode simple }
|
||
|
|
|
||
|
|
proc don { opt } {
|
||
|
|
simdebug set $opt 1
|
||
|
|
}
|
||
|
|
|
||
|
|
proc doff { opt } {
|
||
|
|
simdebug set $opt 0
|
||
|
|
}
|
||
|
|
|
||
|
|
# skisym and linsym return the address of a symbol, looked up from
|
||
|
|
# the relevant System.map or skiboot.map file.
|
||
|
|
proc linsym { name } {
|
||
|
|
global linux_symbol_map
|
||
|
|
|
||
|
|
# create a regexp that matches the symbol name
|
||
|
|
set base {([[:xdigit:]]*) (.)}
|
||
|
|
set exp [concat $base " $name\$"]
|
||
|
|
set ret ""
|
||
|
|
|
||
|
|
foreach {line addr type} [regexp -line -inline $exp $linux_symbol_map] {
|
||
|
|
set ret "0x$addr"
|
||
|
|
}
|
||
|
|
|
||
|
|
return $ret
|
||
|
|
}
|
||
|
|
|
||
|
|
# skisym factors in skiboot's load address
|
||
|
|
proc skisym { name } {
|
||
|
|
global skiboot_symbol_map
|
||
|
|
global mconf
|
||
|
|
|
||
|
|
set base {([[:xdigit:]]*) (.)}
|
||
|
|
set exp [concat $base " $name\$"]
|
||
|
|
set ret ""
|
||
|
|
|
||
|
|
foreach {line addr type} [regexp -line -inline $exp $skiboot_symbol_map] {
|
||
|
|
set actual_addr [expr "0x$addr" + $mconf(boot_load)]
|
||
|
|
set ret [format "0x%.16x" $actual_addr]
|
||
|
|
}
|
||
|
|
|
||
|
|
return $ret
|
||
|
|
}
|
||
|
|
|
||
|
|
proc addr2func { addr } {
|
||
|
|
global skiboot_symbol_list
|
||
|
|
global linux_symbol_list
|
||
|
|
global user_symbol_list
|
||
|
|
global mconf
|
||
|
|
|
||
|
|
set prevname ""
|
||
|
|
set preva "0"
|
||
|
|
|
||
|
|
if { [ info exists linux_symbol_list ] && "$addr" >= 0xc000000000000000} {
|
||
|
|
foreach line $linux_symbol_list {
|
||
|
|
lassign $line a type name
|
||
|
|
if { "0x$a" > $addr } {
|
||
|
|
set o [format "0x%x" [expr $addr - "0x$preva"]]
|
||
|
|
return "$prevname+$o"
|
||
|
|
}
|
||
|
|
set prevname $name
|
||
|
|
set preva $a
|
||
|
|
}
|
||
|
|
}
|
||
|
|
# Assume skiboot is less that 4MB big
|
||
|
|
if { [ info exists skiboot_symbol_list ] &&
|
||
|
|
"$addr" > $mconf(boot_load) && "$addr" < [expr $mconf(boot_load) + 4194304] } {
|
||
|
|
set mapaddr [expr $addr - $mconf(boot_load)]
|
||
|
|
|
||
|
|
foreach line $skiboot_symbol_list {
|
||
|
|
lassign $line a type name
|
||
|
|
if { "0x$a" > $mapaddr } {
|
||
|
|
set o [format "0x%x" [expr $mapaddr - "0x$preva"]]
|
||
|
|
return "$prevname+$o"
|
||
|
|
}
|
||
|
|
set prevname $name
|
||
|
|
set preva $a
|
||
|
|
}
|
||
|
|
}
|
||
|
|
if { [ info exists user_symbol_list ] } {
|
||
|
|
foreach line $user_symbol_list {
|
||
|
|
lassign $line a type name
|
||
|
|
if { "0x$a" > $addr } {
|
||
|
|
set o [format "0x%x" [expr $addr - "0x$preva"]]
|
||
|
|
return "$prevname+$o"
|
||
|
|
}
|
||
|
|
set prevname $name
|
||
|
|
set preva $a
|
||
|
|
}
|
||
|
|
}
|
||
|
|
return "+$addr"
|
||
|
|
}
|
||
|
|
|
||
|
|
proc current_insn { { t -1 } { c -1 } { p -1 }} {
|
||
|
|
global target_t
|
||
|
|
global target_c
|
||
|
|
global target_p
|
||
|
|
|
||
|
|
if { $t == -1 } { set t $target_t }
|
||
|
|
if { $c == -1 } { set c $target_c }
|
||
|
|
if { $p == -1 } { set p $target_p }
|
||
|
|
|
||
|
|
set pc [mysim cpu $p:$c:$t display spr pc]
|
||
|
|
set pc_laddr [mysim cpu $p:$c:$t util itranslate $pc]
|
||
|
|
set inst [mysim cpu $p:$c:$t memory display $pc_laddr 4]
|
||
|
|
set disasm [mysim cpu $p:$c:$t util ppc_disasm $inst $pc]
|
||
|
|
return $disasm
|
||
|
|
}
|
||
|
|
|
||
|
|
set SRR1 0
|
||
|
|
set DSISR 0
|
||
|
|
set DAR 0
|
||
|
|
|
||
|
|
proc sreset_trigger { args } {
|
||
|
|
global SRR1
|
||
|
|
upvar #0 target_t t
|
||
|
|
upvar #0 target_c c
|
||
|
|
upvar #0 target_p p
|
||
|
|
|
||
|
|
mysim trigger clear pc 0x100
|
||
|
|
mysim trigger clear pc 0x104
|
||
|
|
set s [expr [mysim cpu $p:$c:$t display spr srr1] & ~0x00000000003c0002]
|
||
|
|
set SRR1 [expr $SRR1 | $s]
|
||
|
|
mysim cpu $p:$c:$t set spr srr1 $SRR1
|
||
|
|
}
|
||
|
|
|
||
|
|
proc exc_sreset { } {
|
||
|
|
global SRR1
|
||
|
|
global DSISR
|
||
|
|
global DAR
|
||
|
|
upvar #0 target_t t
|
||
|
|
upvar #0 target_c c
|
||
|
|
upvar #0 target_p p
|
||
|
|
|
||
|
|
# In case of recoverable MCE, idle wakeup always sets RI, others get
|
||
|
|
# RI from current environment. For unrecoverable, RI would always be
|
||
|
|
# clear by hardware.
|
||
|
|
if { [current_insn] in { "stop" "nap" "sleep" "winkle" } } {
|
||
|
|
set msr_ri 0x2
|
||
|
|
set SRR1_powersave [expr (0x2 << (63-47))]
|
||
|
|
} else {
|
||
|
|
set msr_ri [expr [mysim cpu $p:$c:$t display spr msr] & 0x2]
|
||
|
|
set SRR1_powersave 0
|
||
|
|
}
|
||
|
|
|
||
|
|
# reason system reset
|
||
|
|
set SRR1_reason 0x4
|
||
|
|
|
||
|
|
set SRR1 [expr 0x0 | $msr_ri | $SRR1_powersave]
|
||
|
|
set SRR1 [expr $SRR1 | ((($SRR1_reason >> 3) & 0x1) << (63-42))]
|
||
|
|
set SRR1 [expr $SRR1 | ((($SRR1_reason >> 2) & 0x1) << (63-43))]
|
||
|
|
set SRR1 [expr $SRR1 | ((($SRR1_reason >> 1) & 0x1) << (63-44))]
|
||
|
|
set SRR1 [expr $SRR1 | ((($SRR1_reason >> 0) & 0x1) << (63-45))]
|
||
|
|
|
||
|
|
if { [current_insn] in { "stop" "nap" "sleep" "winkle" } } {
|
||
|
|
# mambo has a quirk that interrupts from idle wake immediately
|
||
|
|
# and go over current instruction.
|
||
|
|
mysim trigger set pc 0x100 "sreset_trigger"
|
||
|
|
mysim trigger set pc 0x104 "sreset_trigger"
|
||
|
|
mysim cpu $p:$c:$t interrupt SystemReset
|
||
|
|
} else {
|
||
|
|
mysim trigger set pc 0x100 "sreset_trigger"
|
||
|
|
mysim trigger set pc 0x104 "sreset_trigger"
|
||
|
|
mysim cpu $p:$c:$t interrupt SystemReset
|
||
|
|
}
|
||
|
|
|
||
|
|
# sleep and sometimes other types of interrupts do not trigger 0x100
|
||
|
|
if { [expr [mysim cpu $p:$c:$t display spr pc] == 0x100 ] } {
|
||
|
|
sreset_trigger
|
||
|
|
}
|
||
|
|
if { [expr [mysim cpu $p:$c:$t display spr pc] == 0x104 ] } {
|
||
|
|
sreset_trigger
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
proc mce_trigger { args } {
|
||
|
|
global SRR1
|
||
|
|
global DSISR
|
||
|
|
global DAR
|
||
|
|
upvar #0 target_t t
|
||
|
|
upvar #0 target_c c
|
||
|
|
upvar #0 target_p p
|
||
|
|
|
||
|
|
mysim trigger clear pc 0x200
|
||
|
|
mysim trigger clear pc 0x204
|
||
|
|
|
||
|
|
set s [expr [mysim cpu 0 display spr srr1] & ~0x00000000801f0002]
|
||
|
|
set SRR1 [expr $SRR1 | $s]
|
||
|
|
mysim cpu $p:$c:$t set spr srr1 $SRR1
|
||
|
|
mysim cpu $p:$c:$t set spr dsisr $DSISR
|
||
|
|
mysim cpu $p:$c:$t set spr dar $DAR ; list
|
||
|
|
}
|
||
|
|
|
||
|
|
#
|
||
|
|
# Inject a machine check. Recoverable MCE types can be forced to unrecoverable
|
||
|
|
# by clearing MSR_RI bit from SRR1 (which hardware may do).
|
||
|
|
# If d_side is 0, then cause goes into SRR1. Otherwise it gets put into DSISR.
|
||
|
|
# DAR is hardcoded to always 0xdeadbeefdeadbeef
|
||
|
|
#
|
||
|
|
# Default with no arguments is a recoverable i-side TLB multi-hit
|
||
|
|
# Other options:
|
||
|
|
# d_side=1 dsisr=0x80 - recoverable d-side SLB multi-hit
|
||
|
|
# d_side=1 dsisr=0x8000 - ue error on instruction fetch
|
||
|
|
# d_side=0 cause=0xd - unrecoverable i-side async store timeout (POWER9 only)
|
||
|
|
# d_side=0 cause=0x1 - unrecoverable i-side ifetch
|
||
|
|
#
|
||
|
|
proc exc_mce { { d_side 0 } { cause 0x5 } { recoverable 1 } } {
|
||
|
|
global SRR1
|
||
|
|
global DSISR
|
||
|
|
global DAR
|
||
|
|
upvar #0 target_t t
|
||
|
|
upvar #0 target_c c
|
||
|
|
upvar #0 target_p p
|
||
|
|
|
||
|
|
# puts "INJECTING MCE"
|
||
|
|
|
||
|
|
# In case of recoverable MCE, idle wakeup always sets RI, others get
|
||
|
|
# RI from current environment. For unrecoverable, RI would always be
|
||
|
|
# clear by hardware.
|
||
|
|
if { [current_insn] in { "stop" "nap" "sleep" "winkle" } } {
|
||
|
|
set msr_ri 0x2
|
||
|
|
set SRR1_powersave [expr (0x2 << (63-47))]
|
||
|
|
} else {
|
||
|
|
set msr_ri [expr [mysim cpu $p:$c:$t display spr msr] & 0x2]
|
||
|
|
set SRR1_powersave 0
|
||
|
|
}
|
||
|
|
|
||
|
|
if { !$recoverable } {
|
||
|
|
set msr_ri 0x0
|
||
|
|
}
|
||
|
|
|
||
|
|
if { $d_side } {
|
||
|
|
set is_dside 1
|
||
|
|
set SRR1_mc_cause 0x0
|
||
|
|
set DSISR $cause
|
||
|
|
set DAR 0xdeadbeefdeadbeef
|
||
|
|
} else {
|
||
|
|
set is_dside 0
|
||
|
|
set SRR1_mc_cause $cause
|
||
|
|
set DSISR 0x0
|
||
|
|
set DAR 0x0
|
||
|
|
}
|
||
|
|
|
||
|
|
set SRR1 [expr 0x0 | $msr_ri | $SRR1_powersave]
|
||
|
|
|
||
|
|
set SRR1 [expr $SRR1 | ($is_dside << (63-42))]
|
||
|
|
set SRR1 [expr $SRR1 | ((($SRR1_mc_cause >> 3) & 0x1) << (63-36))]
|
||
|
|
set SRR1 [expr $SRR1 | ((($SRR1_mc_cause >> 2) & 0x1) << (63-43))]
|
||
|
|
set SRR1 [expr $SRR1 | ((($SRR1_mc_cause >> 1) & 0x1) << (63-44))]
|
||
|
|
set SRR1 [expr $SRR1 | ((($SRR1_mc_cause >> 0) & 0x1) << (63-45))]
|
||
|
|
|
||
|
|
if { [current_insn] in { "stop" "nap" "sleep" "winkle" } } {
|
||
|
|
# mambo has a quirk that interrupts from idle wake immediately
|
||
|
|
# and go over current instruction.
|
||
|
|
mysim trigger set pc 0x200 "mce_trigger"
|
||
|
|
mysim trigger set pc 0x204 "mce_trigger"
|
||
|
|
mysim cpu $p:$c:$t interrupt MachineCheck
|
||
|
|
} else {
|
||
|
|
mysim trigger set pc 0x200 "mce_trigger"
|
||
|
|
mysim trigger set pc 0x204 "mce_trigger"
|
||
|
|
mysim cpu $p:$c:$t interrupt MachineCheck
|
||
|
|
}
|
||
|
|
|
||
|
|
# sleep and sometimes other types of interrupts do not trigger 0x200
|
||
|
|
if { [expr [mysim cpu $p:$c:$t display spr pc] == 0x200 ] } {
|
||
|
|
mce_trigger
|
||
|
|
}
|
||
|
|
if { [expr [mysim cpu $p:$c:$t display spr pc] == 0x204 ] } {
|
||
|
|
mce_trigger
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
set R1 0
|
||
|
|
|
||
|
|
# Avoid stopping if we re-enter the same code. Wait until r1 matches.
|
||
|
|
# This helps stepping over exceptions or function calls etc.
|
||
|
|
proc stop_stack_match { args } {
|
||
|
|
global R1
|
||
|
|
upvar #0 target_t t
|
||
|
|
upvar #0 target_c c
|
||
|
|
upvar #0 target_p p
|
||
|
|
|
||
|
|
set r1 [mysim cpu $p:$c:$t display gpr 1]
|
||
|
|
if { $R1 == $r1 } {
|
||
|
|
simstop
|
||
|
|
ipca
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
# inject default recoverable MCE and step over it. Useful for testing whether
|
||
|
|
# code copes with taking an interleaving MCE.
|
||
|
|
proc inject_mce { } {
|
||
|
|
global R1
|
||
|
|
upvar #0 target_t t
|
||
|
|
upvar #0 target_c c
|
||
|
|
upvar #0 target_p p
|
||
|
|
|
||
|
|
set R1 [mysim cpu $p:$c:$t display gpr 1]
|
||
|
|
set pc [mysim cpu $p:$c:$t display spr pc]
|
||
|
|
mysim trigger set pc $pc "stop_stack_match"
|
||
|
|
exc_mce
|
||
|
|
c
|
||
|
|
mysim trigger clear pc $pc ; list
|
||
|
|
}
|
||
|
|
|
||
|
|
#
|
||
|
|
# We've stopped at addr and we need to inject the mce and continue
|
||
|
|
#
|
||
|
|
proc trigger_mce_ue_addr {args} {
|
||
|
|
set addr [lindex [lindex $args 0] 1]
|
||
|
|
mysim trigger clear memory system rw $addr $addr
|
||
|
|
exc_mce 0x1 0x8000 0x1
|
||
|
|
}
|
||
|
|
|
||
|
|
proc inject_mce_ue_on_addr {addr} {
|
||
|
|
mysim trigger set memory system rw $addr $addr 1 "trigger_mce_ue_addr"
|
||
|
|
}
|
||
|
|
|
||
|
|
# inject and step over one instruction, and repeat.
|
||
|
|
proc inject_mce_step { {nr 1} } {
|
||
|
|
for { set i 0 } { $i < $nr } { incr i 1 } {
|
||
|
|
inject_mce
|
||
|
|
s
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
# inject if RI is set and step over one instruction, and repeat.
|
||
|
|
proc inject_mce_step_ri { {nr 1} } {
|
||
|
|
upvar #0 target_t t
|
||
|
|
upvar #0 target_c c
|
||
|
|
upvar #0 target_p p
|
||
|
|
|
||
|
|
set reserve_inject 1
|
||
|
|
set reserve_inject_skip 0
|
||
|
|
set reserve_counter 0
|
||
|
|
|
||
|
|
for { set i 0 } { $i < $nr } { incr i 1 } {
|
||
|
|
if { [expr [mysim cpu $p:$c:$t display spr msr] & 0x2] } {
|
||
|
|
# inject_mce
|
||
|
|
if { [mysim cpu $p:$c:$t display reservation] in { "none" } } {
|
||
|
|
inject_mce
|
||
|
|
mysim cpu $p:$c:$t set reservation none
|
||
|
|
if { $reserve_inject_skip } {
|
||
|
|
set reserve_inject 1
|
||
|
|
set reserve_inject_skip 0
|
||
|
|
}
|
||
|
|
} else {
|
||
|
|
if { $reserve_inject } {
|
||
|
|
inject_mce
|
||
|
|
mysim cpu $p:$c:$t set reservation none
|
||
|
|
set reserve_inject 0
|
||
|
|
} else {
|
||
|
|
set reserve_inject_skip 1
|
||
|
|
set reserve_counter [ expr $reserve_counter + 1 ]
|
||
|
|
if { $reserve_counter > 30 } {
|
||
|
|
mysim cpu $p:$c:$t set reservation none
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
s
|
||
|
|
}
|
||
|
|
}
|