260 lines
7.7 KiB
C
260 lines
7.7 KiB
C
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/* Copyright 2013-2016 IBM Corp.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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* implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __NPU2_H
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#define __NPU2_H
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#include <pci.h>
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#include <phys-map.h>
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#include <npu2-regs.h>
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/* Debugging options */
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#define NPU2DBG(p, fmt, a...) prlog(PR_DEBUG, "NPU%d: " fmt, \
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(p)->phb_nvlink.opal_id, ##a)
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#define NPU2INF(p, fmt, a...) prlog(PR_INFO, "NPU%d: " fmt, \
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(p)->phb_nvlink.opal_id, ##a)
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#define NPU2ERR(p, fmt, a...) prlog(PR_ERR, "NPU%d: " fmt, \
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(p)->phb_nvlink.opal_id, ##a)
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#define NPU2DEVLOG(l, p, fmt, a...) prlog(l, "NPU%d:%d:%d.%d " fmt, \
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(p)->npu->phb_nvlink.opal_id, \
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((p)->bdfn >> 8) & 0xff, \
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((p)->bdfn >> 3) & 0x1f, \
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(p)->bdfn & 0x7, ##a)
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#define NPU2DEVDBG(p, fmt, a...) NPU2DEVLOG(PR_DEBUG, p, fmt, ##a)
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#define NPU2DEVINF(p, fmt, a...) NPU2DEVLOG(PR_INFO, p, fmt, ##a)
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#define NPU2DEVERR(p, fmt, a...) NPU2DEVLOG(PR_ERR, p, fmt, ##a)
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#define OCAPIDBG(dev, fmt, a...) prlog(PR_DEBUG, "OCAPI[%d:%d]: " fmt, \
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dev->npu->chip_id, dev->brick_index, ## a)
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#define OCAPIINF(dev, fmt, a...) prlog(PR_INFO, "OCAPI[%d:%d]: " fmt, \
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dev->npu->chip_id, dev->brick_index, ## a)
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#define OCAPIERR(dev, fmt, a...) prlog(PR_ERR, "OCAPI[%d:%d]: " fmt, \
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dev->npu->chip_id, dev->brick_index, ## a)
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/*
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* Number of PEs supported
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*
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* The NPU supports PE numbers from 0-15. At present, we only assign a maximum
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* of 1 PE per brick.
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*
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* NVLink devices are currently exposed to Linux underneath a single virtual
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* PHB. Therefore, we give NVLink half the available PEs, which is enough for
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* 6 bricks plus 1 reserved PE.
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*
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* For OpenCAPI, the BDF-to-PE registers are used exclusively for mapping
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* bricks to System Interrupt Log registers (the BDF component of those
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* registers is ignored). Currently, we allocate a fixed PE based on the brick
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* index in the upper half of the PE namespace.
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*/
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#define NPU2_MAX_PE_NUM 8
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#define NPU2_RESERVED_PE_NUM 7
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#define NPU2_OCAPI_PE(ndev) ((ndev)->brick_index + NPU2_MAX_PE_NUM)
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#define NPU2_LINKS_PER_CHIP 6
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/* Link flags */
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#define NPU2_DEV_PCI_LINKED 0x1
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#define NPU2_DEV_DL_RESET 0x2
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/* Return the stack (0-2) of a device */
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#define NPU2DEV_STACK(ndev) ((ndev)->brick_index / 2)
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/* Return the brick number (0-1) within a stack */
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#define NPU2DEV_BRICK(ndev) ((ndev)->brick_index % 2)
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/* This represents the state of the actual hardware BARs not the
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* emulated PCIe BARs. The is a subtle difference between the two as
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* not all BARs are exposed outside of skiboot. */
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struct npu2_bar {
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enum phys_map_type type;
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int index;
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#define NPU2_BAR_FLAG_ENABLED 0x0010
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/* Generation ID's are a single space in the hardware but we split
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* them in two for the emulated PCIe devices so we need to keep track
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* of which one has been enabled/disabled. */
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#define NPU2_BAR_FLAG_ENABLED0 0x0080
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#define NPU2_BAR_FLAG_ENABLED1 0x0100
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uint32_t flags;
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uint64_t base;
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uint64_t size;
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uint64_t reg;
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};
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/* Rpresents a BAR that is exposed via the PCIe emulated
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* devices */
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struct npu2_pcie_bar {
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#define NPU2_PCIE_BAR_FLAG_SIZE_HI 0x0020
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#define NPU2_PCIE_BAR_FLAG_TRAPPED 0x0040
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uint32_t flags;
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struct npu2_bar npu2_bar;
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};
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enum npu2_dev_type {
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NPU2_DEV_TYPE_UNKNOWN,
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NPU2_DEV_TYPE_NVLINK,
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NPU2_DEV_TYPE_OPENCAPI,
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};
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struct npu2;
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struct npu2_dev_nvlink {
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/* For NVLink, device and function numbers are allocated based
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* on GPU association. Links to connected to the same GPU will
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* be exposed as different functions of the same
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* bus/device. */
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uint32_t gpu_bdfn;
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/* PCI virtual device and the associated GPU device */
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struct pci_virt_device *pvd;
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struct phb *phb;
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struct pci_device *pd;
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uint8_t link_flags;
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/* Used to associate the NPU device with GPU PCI devices */
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const char *slot_label;
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};
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struct npu2_dev {
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enum npu2_dev_type type;
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uint32_t link_index;
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uint32_t brick_index;
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uint64_t pl_xscom_base;
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struct dt_node *dt_node;
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struct npu2_pcie_bar bars[2];
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struct npu2 *npu;
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uint32_t bdfn;
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/* Which PHY lanes this device is associated with */
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uint32_t lane_mask;
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uint64_t link_speed; /* not used for NVLink */
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/* Track currently running procedure and step number */
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uint16_t procedure_number;
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uint16_t procedure_step;
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unsigned long procedure_tb;
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uint32_t procedure_status;
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/* NVLink */
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struct npu2_dev_nvlink nvlink;
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/* OpenCAPI */
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struct phb phb_ocapi;
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uint64_t linux_pe;
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bool train_need_fence;
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bool train_fenced;
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};
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struct npu2 {
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uint32_t index;
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struct dt_node *dt_node;
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uint32_t chip_id;
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uint64_t xscom_base;
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void *regs;
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uint64_t mm_base;
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uint64_t mm_size;
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uint32_t base_lsi;
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uint32_t total_devices;
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struct npu2_dev *devices;
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enum phys_map_type gpu_map_type;
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int ctx_ref[NPU2_XTS_BDF_MAP_SIZE];
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/* IODA cache */
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uint64_t tve_cache[16];
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bool tx_zcal_complete[2];
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/*
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* Used to protect global MMIO space, in particular the XTS
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* tables, and LPC allocation
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*/
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struct lock lock;
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/* NVLink */
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struct phb phb_nvlink;
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uint32_t phb_index;
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/* OCAPI */
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uint64_t i2c_port_id_ocapi;
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struct lock i2c_lock;
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uint8_t i2c_pin_mode;
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uint8_t i2c_pin_wr_state;
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/*
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* Which device currently has an LPC allocation.
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* Temporary as long as we only support 1 LPC alloc per chip.
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*/
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struct npu2_dev *lpc_mem_allocated;
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};
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static inline struct npu2 *phb_to_npu2_nvlink(struct phb *phb)
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{
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assert(phb->phb_type == phb_type_npu_v2);
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return container_of(phb, struct npu2, phb_nvlink);
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}
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static inline struct npu2_dev *phb_to_npu2_dev_ocapi(struct phb *phb)
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{
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assert(phb->phb_type == phb_type_npu_v2_opencapi);
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return container_of(phb, struct npu2_dev, phb_ocapi);
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}
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static inline struct phb *npu2_dev_to_phb(struct npu2_dev *ndev)
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{
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switch (ndev->type) {
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case NPU2_DEV_TYPE_NVLINK:
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return &ndev->npu->phb_nvlink;
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case NPU2_DEV_TYPE_OPENCAPI:
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return &ndev->phb_ocapi;
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default:
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assert(false);
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}
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}
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void npu2_i2c_presence_detect(struct npu2 *npu);
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int npu2_opencapi_init_npu(struct npu2 *npu);
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int npu2_nvlink_init_npu(struct npu2 *npu);
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void npu2_nvlink_create_phb(struct npu2 *npu, struct dt_node *dn);
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void npu2_write_4b(struct npu2 *p, uint64_t reg, uint32_t val);
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uint32_t npu2_read_4b(struct npu2 *p, uint64_t reg);
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void npu2_write(struct npu2 *p, uint64_t reg, uint64_t val);
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uint64_t npu2_read(struct npu2 *p, uint64_t reg);
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void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask);
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void npu2_write_mask_4b(struct npu2 *p, uint64_t reg, uint32_t val, uint32_t mask);
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int64_t npu2_dev_procedure(void *dev, struct pci_cfg_reg_filter *pcrf,
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uint32_t offset, uint32_t len, uint32_t *data,
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bool write);
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void npu2_dev_procedure_reset(struct npu2_dev *dev);
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void npu2_set_link_flag(struct npu2_dev *ndev, uint8_t flag);
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void npu2_clear_link_flag(struct npu2_dev *ndev, uint8_t flag);
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uint32_t reset_ntl(struct npu2_dev *ndev);
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extern int nv_zcal_nominal;
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void npu2_opencapi_phy_init(struct npu2_dev *dev);
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void npu2_opencapi_phy_reset(struct npu2_dev *dev);
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void npu2_opencapi_phy_prbs31(struct npu2_dev *dev);
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void npu2_opencapi_bump_ui_lane(struct npu2_dev *dev);
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int64_t npu2_freeze_status(struct phb *phb __unused,
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uint64_t pe_number __unused,
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uint8_t *freeze_state,
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uint16_t *pci_error_type __unused,
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uint16_t *severity __unused);
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void npu2_dump_scoms(int chip_id);
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#endif /* __NPU2_H */
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