67 lines
1.3 KiB
Text
67 lines
1.3 KiB
Text
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 NXP
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*/
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#include <dt-bindings/clock/imx8qxp-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/{
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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/* We have 1 clusters having 4 Cortex-A35 cores */
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A35_0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0x0 0x0>;
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enable-method = "psci";
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next-level-cache = <&A35_L2>;
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};
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A35_1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0x0 0x1>;
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enable-method = "psci";
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next-level-cache = <&A35_L2>;
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};
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A35_2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0x0 0x2>;
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enable-method = "psci";
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next-level-cache = <&A35_L2>;
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};
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A35_3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0x0 0x3>;
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enable-method = "psci";
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next-level-cache = <&A35_L2>;
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};
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A35_L2: l2-cache0 {
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compatible = "cache";
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};
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_PPI 7
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(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
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interrupt-affinity = <&A35_0>, <&A35_1>, <&A35_2>, <&A35_3>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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cpu_suspend = <0xc4000001>;
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cpu_off = <0xc4000002>;
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cpu_on = <0xc4000003>;
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};
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};
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