339 lines
9.4 KiB
Text
339 lines
9.4 KiB
Text
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#include "skeleton.dtsi"
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#include <dt-bindings/clock/tegra186-clock.h>
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#include <dt-bindings/gpio/tegra186-gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/mailbox/tegra186-hsp.h>
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#include <dt-bindings/power/tegra186-powergate.h>
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#include <dt-bindings/reset/tegra186-reset.h>
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/ {
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compatible = "nvidia,tegra186";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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gpio_main: gpio@2200000 {
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compatible = "nvidia,tegra186-gpio";
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reg-names = "security", "gpio";
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reg =
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<0x0 0x2200000 0x0 0x10000>,
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<0x0 0x2210000 0x0 0x10000>;
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interrupts =
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<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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ethernet@2490000 {
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compatible = "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10";
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reg = <0x0 0x02490000 0x0 0x10000>;
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interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
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<&bpmp TEGRA186_CLK_EQOS_AXI>,
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<&bpmp TEGRA186_CLK_EQOS_RX>,
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<&bpmp TEGRA186_CLK_EQOS_PTP_REF>,
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<&bpmp TEGRA186_CLK_EQOS_TX>;
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clock-names = "slave_bus",
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"master_bus",
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"rx",
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"ptp_ref",
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"tx";
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resets = <&bpmp TEGRA186_RESET_EQOS>;
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reset-names = "eqos";
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phy-mode = "rgmii";
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status = "disabled";
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};
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uarta: serial@3100000 {
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compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
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reg = <0x0 0x03100000 0x0 0x10000>;
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reg-shift = <2>;
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status = "disabled";
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};
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gen1_i2c: i2c@3160000 {
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compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
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reg = <0x0 0x3160000 0x0 0x100>;
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interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp TEGRA186_CLK_I2C1>;
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clock-names = "div-clk";
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resets = <&bpmp TEGRA186_RESET_I2C1>;
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reset-names = "i2c";
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status = "disabled";
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};
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cam_i2c: i2c@3180000 {
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compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
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reg = <0x0 0x3180000 0x0 0x100>;
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interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp TEGRA186_CLK_I2C3>;
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clock-names = "div-clk";
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resets = <&bpmp TEGRA186_RESET_I2C3>;
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reset-names = "i2c";
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status = "disabled";
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};
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dp_aux_ch1_i2c: i2c@3190000 {
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compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
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reg = <0x0 0x3190000 0x0 0x100>;
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp TEGRA186_CLK_I2C4>;
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clock-names = "div-clk";
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resets = <&bpmp TEGRA186_RESET_I2C4>;
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reset-names = "i2c";
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status = "disabled";
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};
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dp_aux_ch0_i2c: i2c@31b0000 {
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compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
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reg = <0x0 0x31b0000 0x0 0x100>;
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp TEGRA186_CLK_I2C6>;
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clock-names = "div-clk";
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resets = <&bpmp TEGRA186_RESET_I2C6>;
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reset-names = "i2c";
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status = "disabled";
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};
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gen7_i2c: i2c@31c0000 {
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compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
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reg = <0x0 0x31c0000 0x0 0x100>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp TEGRA186_CLK_I2C7>;
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clock-names = "div-clk";
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resets = <&bpmp TEGRA186_RESET_I2C7>;
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reset-names = "i2c";
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status = "disabled";
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};
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gen9_i2c: i2c@31e0000 {
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compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
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reg = <0x0 0x31e0000 0x0 0x100>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp TEGRA186_CLK_I2C9>;
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clock-names = "div-clk";
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resets = <&bpmp TEGRA186_RESET_I2C9>;
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reset-names = "i2c";
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status = "disabled";
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};
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sdhci@3400000 {
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compatible = "nvidia,tegra186-sdhci";
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reg = <0x0 0x03400000 0x0 0x200>;
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resets = <&bpmp TEGRA186_RESET_SDMMC1>;
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reset-names = "sdhci";
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clocks = <&bpmp TEGRA186_CLK_SDMMC1>;
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interrupts = <GIC_SPI 62 0x04>;
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status = "disabled";
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};
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sdhci@3460000 {
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compatible = "nvidia,tegra186-sdhci";
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reg = <0x0 0x03460000 0x0 0x200>;
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resets = <&bpmp TEGRA186_RESET_SDMMC4>;
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reset-names = "sdhci";
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clocks = <&bpmp TEGRA186_CLK_SDMMC4>;
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interrupts = <GIC_SPI 31 0x04>;
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status = "disabled";
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};
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gic: interrupt-controller@3881000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x0 0x3881000 0x0 0x1000>,
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<0x0 0x3882000 0x0 0x2000>,
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<0x0 0x3884000 0x0 0x2000>,
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<0x0 0x3886000 0x0 0x2000>;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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interrupt-parent = <&gic>;
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};
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hsp: hsp@3c00000 {
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compatible = "nvidia,tegra186-hsp";
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reg = <0x0 0x03c00000 0x0 0xa0000>;
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interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "doorbell";
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#mbox-cells = <2>;
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};
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gen2_i2c: i2c@c240000 {
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compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
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reg = <0x0 0xc240000 0x0 0x100>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp TEGRA186_CLK_I2C2>;
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clock-names = "div-clk";
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resets = <&bpmp TEGRA186_RESET_I2C2>;
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reset-names = "i2c";
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status = "disabled";
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};
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gen8_i2c: i2c@c250000 {
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compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
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reg = <0x0 0xc250000 0x0 0x100>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp TEGRA186_CLK_I2C8>;
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clock-names = "div-clk";
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resets = <&bpmp TEGRA186_RESET_I2C8>;
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reset-names = "i2c";
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status = "disabled";
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};
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gpio_aon: gpio@c2f0000 {
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compatible = "nvidia,tegra186-gpio-aon";
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reg-names = "security", "gpio";
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reg =
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<0x0 0xc2f0000 0x0 0x1000>,
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<0x0 0xc2f1000 0x0 0x1000>;
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interrupts =
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<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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pcie-controller@10003000 {
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compatible = "nvidia,tegra186-pcie";
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device_type = "pci";
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reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */
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0x0 0x10003800 0x0 0x00000800 /* AFI registers */
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0x0 0x40000000 0x0 0x10000000>; /* configuration space */
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reg-names = "pads", "afi", "cs";
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
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<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, /* MSI interrupt */
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<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; /* Wake interrupt */
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interrupt-names = "intr", "msi", "wake";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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bus-range = <0x00 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */
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0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */
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0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */
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0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */
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0x82000000 0 0x50100000 0x0 0x50100000 0 0x07f00000 /* non-prefetchable memory (127 MiB) */
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0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
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clocks = <&bpmp TEGRA186_CLK_PCIE>,
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<&bpmp TEGRA186_CLK_AFI>;
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clock-names = "pex", "afi";
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resets = <&bpmp TEGRA186_RESET_PCIE>,
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<&bpmp TEGRA186_RESET_AFI>,
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<&bpmp TEGRA186_RESET_PCIEXCLK>;
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reset-names = "pex", "afi", "pcie_x";
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power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
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status = "disabled";
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pci@1,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
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reg = <0x000800 0 0 0 0>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <2>;
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};
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pci@2,0 {
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device_type = "pci";
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assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
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reg = <0x001000 0 0 0 0>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <1>;
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};
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pci@3,0 {
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device_type = "pci";
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assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
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reg = <0x001800 0 0 0 0>;
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status = "disabled";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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nvidia,num-lanes = <1>;
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};
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};
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sysram@30000000 {
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compatible = "nvidia,tegra186-sysram", "mmio-sram";
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reg = <0x0 0x30000000 0x0 0x50000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
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sysram_cpu_bpmp_tx: shmem@4e000 {
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compatible = "nvidia,tegra186-bpmp-shmem";
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reg = <0x0 0x4e000 0x0 0x1000>;
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};
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sysram_cpu_bpmp_rx: shmem@4f000 {
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compatible = "nvidia,tegra186-bpmp-shmem";
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reg = <0x0 0x4f000 0x0 0x1000>;
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};
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};
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bpmp: bpmp {
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compatible = "nvidia,tegra186-bpmp";
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mboxes = <&hsp HSP_MBOX_TYPE_DB HSP_DB_MASTER_BPMP>;
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/*
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* In theory, these references, and the configuration in the
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* node these reference point at, are board-specific, since
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* they depend on the BCT's memory carve-out setup, the
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* firmware that's actually loaded onto the BPMP, etc. However,
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* in practice, all boards are likely to use identical values.
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*/
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shmem = <&sysram_cpu_bpmp_tx &sysram_cpu_bpmp_rx>;
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#clock-cells = <1>;
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#power-domain-cells = <1>;
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#reset-cells = <1>;
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bpmp_i2c: i2c {
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||
|
|
compatible = "nvidia,tegra186-bpmp-i2c";
|
||
|
|
nvidia,bpmp-bus-id = <5>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|