69 lines
1.1 KiB
Text
69 lines
1.1 KiB
Text
|
// SPDX-License-Identifier: GPL-2.0+
|
||
|
|
/*
|
||
|
|
* dts file for Xilinx ZynqMP Mini Configuration
|
||
|
|
*
|
||
|
|
* (C) Copyright 2018, Xilinx, Inc.
|
||
|
|
*
|
||
|
|
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
|
||
|
|
*/
|
||
|
|
|
||
|
|
/dts-v1/;
|
||
|
|
|
||
|
|
/ {
|
||
|
|
model = "ZynqMP MINI EMMC0";
|
||
|
|
compatible = "xlnx,zynqmp";
|
||
|
|
#address-cells = <2>;
|
||
|
|
#size-cells = <2>;
|
||
|
|
|
||
|
|
aliases {
|
||
|
|
serial0 = &dcc;
|
||
|
|
mmc0 = &sdhci0;
|
||
|
|
};
|
||
|
|
|
||
|
|
chosen {
|
||
|
|
stdout-path = "serial0:115200n8";
|
||
|
|
};
|
||
|
|
|
||
|
|
memory@0 {
|
||
|
|
device_type = "memory";
|
||
|
|
reg = <0x0 0x0 0x0 0x20000000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
dcc: dcc {
|
||
|
|
compatible = "arm,dcc";
|
||
|
|
status = "disabled";
|
||
|
|
u-boot,dm-pre-reloc;
|
||
|
|
};
|
||
|
|
|
||
|
|
clk_xin: clk_xin {
|
||
|
|
compatible = "fixed-clock";
|
||
|
|
#clock-cells = <0>;
|
||
|
|
clock-frequency = <200000000>;
|
||
|
|
};
|
||
|
|
|
||
|
|
amba: amba {
|
||
|
|
compatible = "simple-bus";
|
||
|
|
#address-cells = <2>;
|
||
|
|
#size-cells = <2>;
|
||
|
|
ranges;
|
||
|
|
|
||
|
|
sdhci0: sdhci@ff160000 {
|
||
|
|
u-boot,dm-pre-reloc;
|
||
|
|
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
|
||
|
|
status = "disabled";
|
||
|
|
reg = <0x0 0xff160000 0x0 0x1000>;
|
||
|
|
clock-names = "clk_xin", "clk_ahb";
|
||
|
|
clocks = <&clk_xin &clk_xin>;
|
||
|
|
xlnx,device_id = <0>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
&dcc {
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&sdhci0 {
|
||
|
|
status = "okay";
|
||
|
|
};
|