74 lines
1.2 KiB
C
74 lines
1.2 KiB
C
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/types.h>
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#include <mach/tlb.h>
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#include <mach/ddr.h>
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DECLARE_GLOBAL_DATA_PTR;
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static inline int vcoreiii_train_bytelane(void)
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{
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int ret;
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ret = hal_vcoreiii_train_bytelane(0);
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#ifdef CONFIG_SOC_OCELOT
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if (ret)
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return ret;
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ret = hal_vcoreiii_train_bytelane(1);
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#endif
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return ret;
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}
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int vcoreiii_ddr_init(void)
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{
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int res;
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if (!(readl(BASE_CFG + ICPU_MEMCTRL_STAT)
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& ICPU_MEMCTRL_STAT_INIT_DONE)) {
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hal_vcoreiii_init_memctl();
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hal_vcoreiii_wait_memctl();
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if (hal_vcoreiii_init_dqs() || vcoreiii_train_bytelane())
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hal_vcoreiii_ddr_failed();
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}
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#if (CONFIG_SYS_TEXT_BASE != 0x20000000)
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res = dram_check();
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if (res == 0)
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hal_vcoreiii_ddr_verified();
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else
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hal_vcoreiii_ddr_failed();
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/* Clear boot-mode and read-back to activate/verify */
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clrbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
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ICPU_GENERAL_CTRL_BOOT_MODE_ENA);
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readl(BASE_CFG + ICPU_GENERAL_CTRL);
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#else
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res = 0;
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#endif
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return res;
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}
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int print_cpuinfo(void)
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{
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printf("MSCC VCore-III MIPS 24Kec\n");
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return 0;
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}
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int dram_init(void)
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{
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while (vcoreiii_ddr_init())
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;
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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return 0;
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}
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