75 lines
3.1 KiB
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75 lines
3.1 KiB
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.. _skiboot-5.9-rc5:
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skiboot-5.9-rc5
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===============
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skiboot v5.9-rc5 was released on Monday October 23rd 2017 approximately
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32,000ft above somewhere north of Tucson, Arizona. It is the fifth
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release candidate of skiboot 5.9, which will become the new stable release
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of skiboot following the 5.8 release, first released August 31st 2017.
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skiboot v5.9-rc5 contains all bug fixes as of :ref:`skiboot-5.4.8`
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and :ref:`skiboot-5.1.21` (the currently maintained stable releases). We
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do not currently expect to do any 5.8.x stable releases.
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For how the skiboot stable releases work, see :ref:`stable-rules` for details.
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The current plan is to cut the final 5.9 very shortly, with skiboot 5.9
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being for all POWER8 and POWER9 platforms in op-build v1.20 (Due October 18th,
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so we're running a bit behind there).
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This release will be targetted to early POWER9 systems.
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Over :ref:`skiboot-5.9-rc3`, we have the following changes:
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- opal/hmi: Workaround Power9 hw logic bug for couple of TFMR TB errors.
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- opal/hmi: Fix TB reside and HDEC parity error recovery for power9
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- phb4: Escalate freeze to fence to avoid checkstop
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Freeze events such as MMIO loads can cause the PHB to lose it's
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limited powerbus credits. If all credits are used and a further MMIO
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will cause a checkstop.
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To work around this, we escalate the troublesome freeze events to a
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fence. The fence will cause a full PHB reset which resets the powerbus
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credits and avoids the checkstop.
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- phb4: Update some init registers
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New inits based on next PHB4 workbook. Increases some timeouts to
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avoid some spurious error conditions.
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- phb4: Enable PHB MMIO in phb4_root_port_init()
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Linux EEH flow is somewhat broken. It saves the PCIe config space of
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the PHB on boot, which it then uses to restore on EEH recovery. It
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does this to restore MMIO bars and some other pieces.
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Unfortunately this save is done before any drivers are bound to
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devices under the PHB. A number of other things are configured in the
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PHB after drivers start, hence some configuration space settings
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aren't saved correctly. These include bus master and MMIO bits in the
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command register.
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Linux tried to hack around this in this linux commit
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``bf898ec5cb`` powerpc/eeh: Enable PCI_COMMAND_MASTER for PCI bridges
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This sets the bus master bit but ignores the MMIO bit.
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Hence we lose MMIO after a full PHB reset. This causes the next MMIO
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access to the device to fail and for us to perform a PE freeze
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recovery, which still doesn't set the MMIO bit and hence we still
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fail.
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This works around this by forcing MMIO on during
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phb4_root_port_init().
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With this we can recovery from a PHB fence event on POWER9.
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- phb4: Reduce link degraded message log level to debug
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If we hit this message we'll retry and fix the problem. If we run out
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of retries and can't fix the problem, we'll still print a log message
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at error level indicating a problem.
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- phb4: Fix GEN3 for DD2.00
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In this fix: ``62ac7631ae`` "phb4: Fix PCIe GEN4 on DD2.1 and above",
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We fixed DD2.1 GEN4 but broke DD2.00 as GEN3.
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This fixes DD2.00 back to GEN3. This time for sure!
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