425 lines
11 KiB
C
425 lines
11 KiB
C
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//===-- MipsInstPrinter.cpp - Convert Mips MCInst to assembly syntax ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This class prints an Mips MCInst to a .s file.
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//
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//===----------------------------------------------------------------------===//
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/* Capstone Disassembly Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
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#ifdef CAPSTONE_HAS_MIPS
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#include <platform.h>
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#include <stdlib.h>
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#include <stdio.h> // debug
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#include <string.h>
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#include "MipsInstPrinter.h"
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#include "../../MCInst.h"
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#include "../../utils.h"
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#include "../../SStream.h"
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#include "../../MCRegisterInfo.h"
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#include "MipsMapping.h"
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#include "MipsInstPrinter.h"
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static void printUnsignedImm(MCInst *MI, int opNum, SStream *O);
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static char *printAliasInstr(MCInst *MI, SStream *O, void *info);
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static char *printAlias(MCInst *MI, SStream *OS);
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// These enumeration declarations were originally in MipsInstrInfo.h but
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// had to be moved here to avoid circular dependencies between
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// LLVMMipsCodeGen and LLVMMipsAsmPrinter.
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// Mips Condition Codes
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typedef enum Mips_CondCode {
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// To be used with float branch True
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Mips_FCOND_F,
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Mips_FCOND_UN,
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Mips_FCOND_OEQ,
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Mips_FCOND_UEQ,
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Mips_FCOND_OLT,
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Mips_FCOND_ULT,
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Mips_FCOND_OLE,
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Mips_FCOND_ULE,
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Mips_FCOND_SF,
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Mips_FCOND_NGLE,
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Mips_FCOND_SEQ,
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Mips_FCOND_NGL,
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Mips_FCOND_LT,
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Mips_FCOND_NGE,
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Mips_FCOND_LE,
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Mips_FCOND_NGT,
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// To be used with float branch False
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// This conditions have the same mnemonic as the
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// above ones, but are used with a branch False;
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Mips_FCOND_T,
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Mips_FCOND_OR,
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Mips_FCOND_UNE,
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Mips_FCOND_ONE,
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Mips_FCOND_UGE,
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Mips_FCOND_OGE,
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Mips_FCOND_UGT,
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Mips_FCOND_OGT,
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Mips_FCOND_ST,
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Mips_FCOND_GLE,
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Mips_FCOND_SNE,
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Mips_FCOND_GL,
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Mips_FCOND_NLT,
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Mips_FCOND_GE,
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Mips_FCOND_NLE,
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Mips_FCOND_GT
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} Mips_CondCode;
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#define GET_INSTRINFO_ENUM
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#include "MipsGenInstrInfo.inc"
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static const char *getRegisterName(unsigned RegNo);
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static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI);
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static void set_mem_access(MCInst *MI, bool status)
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{
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MI->csh->doing_mem = status;
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if (MI->csh->detail != CS_OPT_ON)
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return;
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if (status) {
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MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_MEM;
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MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.base = MIPS_REG_INVALID;
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MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.disp = 0;
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} else {
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// done, create the next operand slot
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MI->flat_insn->detail->mips.op_count++;
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}
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}
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static bool isReg(MCInst *MI, unsigned OpNo, unsigned R)
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{
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return (MCOperand_isReg(MCInst_getOperand(MI, OpNo)) &&
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MCOperand_getReg(MCInst_getOperand(MI, OpNo)) == R);
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}
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static const char* MipsFCCToString(Mips_CondCode CC)
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{
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switch (CC) {
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default: return 0; // never reach
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case Mips_FCOND_F:
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case Mips_FCOND_T: return "f";
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case Mips_FCOND_UN:
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case Mips_FCOND_OR: return "un";
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case Mips_FCOND_OEQ:
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case Mips_FCOND_UNE: return "eq";
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case Mips_FCOND_UEQ:
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case Mips_FCOND_ONE: return "ueq";
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case Mips_FCOND_OLT:
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case Mips_FCOND_UGE: return "olt";
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case Mips_FCOND_ULT:
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case Mips_FCOND_OGE: return "ult";
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case Mips_FCOND_OLE:
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case Mips_FCOND_UGT: return "ole";
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case Mips_FCOND_ULE:
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case Mips_FCOND_OGT: return "ule";
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case Mips_FCOND_SF:
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case Mips_FCOND_ST: return "sf";
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case Mips_FCOND_NGLE:
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case Mips_FCOND_GLE: return "ngle";
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case Mips_FCOND_SEQ:
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case Mips_FCOND_SNE: return "seq";
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case Mips_FCOND_NGL:
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case Mips_FCOND_GL: return "ngl";
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case Mips_FCOND_LT:
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case Mips_FCOND_NLT: return "lt";
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case Mips_FCOND_NGE:
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case Mips_FCOND_GE: return "nge";
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case Mips_FCOND_LE:
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case Mips_FCOND_NLE: return "le";
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case Mips_FCOND_NGT:
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case Mips_FCOND_GT: return "ngt";
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}
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}
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static void printRegName(SStream *OS, unsigned RegNo)
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{
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SStream_concat(OS, "$%s", getRegisterName(RegNo));
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}
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void Mips_printInst(MCInst *MI, SStream *O, void *info)
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{
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char *mnem;
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switch (MCInst_getOpcode(MI)) {
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default: break;
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case Mips_Save16:
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case Mips_SaveX16:
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case Mips_Restore16:
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case Mips_RestoreX16:
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return;
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}
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// Try to print any aliases first.
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mnem = printAliasInstr(MI, O, info);
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if (!mnem) {
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mnem = printAlias(MI, O);
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if (!mnem) {
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printInstruction(MI, O, NULL);
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}
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}
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if (mnem) {
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// fixup instruction id due to the change in alias instruction
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MCInst_setOpcodePub(MI, Mips_map_insn(mnem));
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cs_mem_free(mnem);
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}
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}
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static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
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{
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MCOperand *Op;
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if (OpNo >= MI->size)
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return;
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Op = MCInst_getOperand(MI, OpNo);
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if (MCOperand_isReg(Op)) {
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unsigned int reg = MCOperand_getReg(Op);
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printRegName(O, reg);
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reg = Mips_map_register(reg);
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if (MI->csh->detail) {
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if (MI->csh->doing_mem) {
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MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.base = reg;
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} else {
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MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_REG;
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MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].reg = reg;
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MI->flat_insn->detail->mips.op_count++;
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}
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}
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} else if (MCOperand_isImm(Op)) {
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int64_t imm = MCOperand_getImm(Op);
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if (MI->csh->doing_mem) {
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if (imm) { // only print Imm offset if it is not 0
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if (imm >= 0) {
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if (imm > HEX_THRESHOLD)
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SStream_concat(O, "0x%"PRIx64, imm);
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else
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SStream_concat(O, "%"PRIu64, imm);
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} else {
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if (imm < -HEX_THRESHOLD)
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SStream_concat(O, "-0x%"PRIx64, -imm);
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else
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SStream_concat(O, "-%"PRIu64, -imm);
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}
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}
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if (MI->csh->detail)
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MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.disp = imm;
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} else {
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if (imm >= 0) {
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if (imm > HEX_THRESHOLD)
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SStream_concat(O, "0x%"PRIx64, imm);
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else
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SStream_concat(O, "%"PRIu64, imm);
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} else {
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if (imm < -HEX_THRESHOLD)
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SStream_concat(O, "-0x%"PRIx64, -imm);
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else
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SStream_concat(O, "-%"PRIu64, -imm);
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}
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if (MI->csh->detail) {
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MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM;
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MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = imm;
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MI->flat_insn->detail->mips.op_count++;
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}
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}
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}
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}
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static void printUnsignedImm(MCInst *MI, int opNum, SStream *O)
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{
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MCOperand *MO = MCInst_getOperand(MI, opNum);
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if (MCOperand_isImm(MO)) {
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int64_t imm = MCOperand_getImm(MO);
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if (imm >= 0) {
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if (imm > HEX_THRESHOLD)
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SStream_concat(O, "0x%x", (unsigned short int)imm);
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else
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SStream_concat(O, "%u", (unsigned short int)imm);
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} else {
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if (imm < -HEX_THRESHOLD)
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SStream_concat(O, "-0x%x", (short int)-imm);
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else
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SStream_concat(O, "-%u", (short int)-imm);
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}
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if (MI->csh->detail) {
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MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM;
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MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = (unsigned short int)imm;
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MI->flat_insn->detail->mips.op_count++;
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}
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} else
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printOperand(MI, opNum, O);
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}
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static void printUnsignedImm8(MCInst *MI, int opNum, SStream *O)
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{
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MCOperand *MO = MCInst_getOperand(MI, opNum);
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if (MCOperand_isImm(MO)) {
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uint8_t imm = (uint8_t)MCOperand_getImm(MO);
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if (imm > HEX_THRESHOLD)
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SStream_concat(O, "0x%x", imm);
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else
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SStream_concat(O, "%u", imm);
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if (MI->csh->detail) {
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MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_IMM;
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MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].imm = imm;
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MI->flat_insn->detail->mips.op_count++;
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}
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} else
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printOperand(MI, opNum, O);
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}
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static void printMemOperand(MCInst *MI, int opNum, SStream *O)
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{
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// Load/Store memory operands -- imm($reg)
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// If PIC target the target is loaded as the
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// pattern lw $25,%call16($28)
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set_mem_access(MI, true);
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printOperand(MI, opNum + 1, O);
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SStream_concat0(O, "(");
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printOperand(MI, opNum, O);
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SStream_concat0(O, ")");
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set_mem_access(MI, false);
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}
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// TODO???
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static void printMemOperandEA(MCInst *MI, int opNum, SStream *O)
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{
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// when using stack locations for not load/store instructions
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// print the same way as all normal 3 operand instructions.
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printOperand(MI, opNum, O);
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SStream_concat0(O, ", ");
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printOperand(MI, opNum + 1, O);
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return;
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}
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static void printFCCOperand(MCInst *MI, int opNum, SStream *O)
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{
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MCOperand *MO = MCInst_getOperand(MI, opNum);
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SStream_concat0(O, MipsFCCToString((Mips_CondCode)MCOperand_getImm(MO)));
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}
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static char *printAlias1(const char *Str, MCInst *MI, unsigned OpNo, SStream *OS)
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{
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SStream_concat(OS, "%s\t", Str);
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printOperand(MI, OpNo, OS);
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return cs_strdup(Str);
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}
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static char *printAlias2(const char *Str, MCInst *MI,
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unsigned OpNo0, unsigned OpNo1, SStream *OS)
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{
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char *tmp;
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tmp = printAlias1(Str, MI, OpNo0, OS);
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SStream_concat0(OS, ", ");
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printOperand(MI, OpNo1, OS);
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return tmp;
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}
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#define GET_REGINFO_ENUM
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#include "MipsGenRegisterInfo.inc"
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static char *printAlias(MCInst *MI, SStream *OS)
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{
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switch (MCInst_getOpcode(MI)) {
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case Mips_BEQ:
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// beq $zero, $zero, $L2 => b $L2
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// beq $r0, $zero, $L2 => beqz $r0, $L2
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|
if (isReg(MI, 0, Mips_ZERO) && isReg(MI, 1, Mips_ZERO))
|
||
|
|
return printAlias1("b", MI, 2, OS);
|
||
|
|
if (isReg(MI, 1, Mips_ZERO))
|
||
|
|
return printAlias2("beqz", MI, 0, 2, OS);
|
||
|
|
return NULL;
|
||
|
|
case Mips_BEQL:
|
||
|
|
// beql $r0, $zero, $L2 => beqzl $r0, $L2
|
||
|
|
if (isReg(MI, 0, Mips_ZERO) && isReg(MI, 1, Mips_ZERO))
|
||
|
|
return printAlias2("beqzl", MI, 0, 2, OS);
|
||
|
|
return NULL;
|
||
|
|
case Mips_BEQ64:
|
||
|
|
// beq $r0, $zero, $L2 => beqz $r0, $L2
|
||
|
|
if (isReg(MI, 1, Mips_ZERO_64))
|
||
|
|
return printAlias2("beqz", MI, 0, 2, OS);
|
||
|
|
return NULL;
|
||
|
|
case Mips_BNE:
|
||
|
|
// bne $r0, $zero, $L2 => bnez $r0, $L2
|
||
|
|
if (isReg(MI, 1, Mips_ZERO))
|
||
|
|
return printAlias2("bnez", MI, 0, 2, OS);
|
||
|
|
return NULL;
|
||
|
|
case Mips_BNEL:
|
||
|
|
// bnel $r0, $zero, $L2 => bnezl $r0, $L2
|
||
|
|
if (isReg(MI, 1, Mips_ZERO))
|
||
|
|
return printAlias2("bnezl", MI, 0, 2, OS);
|
||
|
|
return NULL;
|
||
|
|
case Mips_BNE64:
|
||
|
|
// bne $r0, $zero, $L2 => bnez $r0, $L2
|
||
|
|
if (isReg(MI, 1, Mips_ZERO_64))
|
||
|
|
return printAlias2("bnez", MI, 0, 2, OS);
|
||
|
|
return NULL;
|
||
|
|
case Mips_BGEZAL:
|
||
|
|
// bgezal $zero, $L1 => bal $L1
|
||
|
|
if (isReg(MI, 0, Mips_ZERO))
|
||
|
|
return printAlias1("bal", MI, 1, OS);
|
||
|
|
return NULL;
|
||
|
|
case Mips_BC1T:
|
||
|
|
// bc1t $fcc0, $L1 => bc1t $L1
|
||
|
|
if (isReg(MI, 0, Mips_FCC0))
|
||
|
|
return printAlias1("bc1t", MI, 1, OS);
|
||
|
|
return NULL;
|
||
|
|
case Mips_BC1F:
|
||
|
|
// bc1f $fcc0, $L1 => bc1f $L1
|
||
|
|
if (isReg(MI, 0, Mips_FCC0))
|
||
|
|
return printAlias1("bc1f", MI, 1, OS);
|
||
|
|
return NULL;
|
||
|
|
case Mips_JALR:
|
||
|
|
// jalr $ra, $r1 => jalr $r1
|
||
|
|
if (isReg(MI, 0, Mips_RA))
|
||
|
|
return printAlias1("jalr", MI, 1, OS);
|
||
|
|
return NULL;
|
||
|
|
case Mips_JALR64:
|
||
|
|
// jalr $ra, $r1 => jalr $r1
|
||
|
|
if (isReg(MI, 0, Mips_RA_64))
|
||
|
|
return printAlias1("jalr", MI, 1, OS);
|
||
|
|
return NULL;
|
||
|
|
case Mips_NOR:
|
||
|
|
case Mips_NOR_MM:
|
||
|
|
// nor $r0, $r1, $zero => not $r0, $r1
|
||
|
|
if (isReg(MI, 2, Mips_ZERO))
|
||
|
|
return printAlias2("not", MI, 0, 1, OS);
|
||
|
|
return NULL;
|
||
|
|
case Mips_NOR64:
|
||
|
|
// nor $r0, $r1, $zero => not $r0, $r1
|
||
|
|
if (isReg(MI, 2, Mips_ZERO_64))
|
||
|
|
return printAlias2("not", MI, 0, 1, OS);
|
||
|
|
return NULL;
|
||
|
|
case Mips_OR:
|
||
|
|
// or $r0, $r1, $zero => move $r0, $r1
|
||
|
|
if (isReg(MI, 2, Mips_ZERO))
|
||
|
|
return printAlias2("move", MI, 0, 1, OS);
|
||
|
|
return NULL;
|
||
|
|
default: return NULL;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
#define PRINT_ALIAS_INSTR
|
||
|
|
#include "MipsGenAsmWriter.inc"
|
||
|
|
|
||
|
|
#endif
|