237 lines
4.7 KiB
C
237 lines
4.7 KiB
C
#ifndef CAPSTONE_XCORE_H
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#define CAPSTONE_XCORE_H
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/* Capstone Disassembly Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2014 */
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
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#include <stdint.h>
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#endif
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#include "platform.h"
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#ifdef _MSC_VER
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#pragma warning(disable:4201)
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#endif
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//> Operand type for instruction's operands
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typedef enum xcore_op_type {
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XCORE_OP_INVALID = 0, // = CS_OP_INVALID (Uninitialized).
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XCORE_OP_REG, // = CS_OP_REG (Register operand).
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XCORE_OP_IMM, // = CS_OP_IMM (Immediate operand).
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XCORE_OP_MEM, // = CS_OP_MEM (Memory operand).
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} xcore_op_type;
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// Instruction's operand referring to memory
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// This is associated with XCORE_OP_MEM operand type above
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typedef struct xcore_op_mem {
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uint8_t base; // base register
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uint8_t index; // index register
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int32_t disp; // displacement/offset value
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int direct; // +1: forward, -1: backward
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} xcore_op_mem;
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// Instruction operand
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typedef struct cs_xcore_op {
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xcore_op_type type; // operand type
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union {
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unsigned int reg; // register value for REG operand
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int32_t imm; // immediate value for IMM operand
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xcore_op_mem mem; // base/disp value for MEM operand
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};
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} cs_xcore_op;
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// Instruction structure
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typedef struct cs_xcore {
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// Number of operands of this instruction,
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// or 0 when instruction has no operand.
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uint8_t op_count;
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cs_xcore_op operands[8]; // operands for this instruction.
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} cs_xcore;
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//> XCore registers
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typedef enum xcore_reg {
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XCORE_REG_INVALID = 0,
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XCORE_REG_CP,
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XCORE_REG_DP,
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XCORE_REG_LR,
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XCORE_REG_SP,
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XCORE_REG_R0,
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XCORE_REG_R1,
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XCORE_REG_R2,
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XCORE_REG_R3,
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XCORE_REG_R4,
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XCORE_REG_R5,
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XCORE_REG_R6,
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XCORE_REG_R7,
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XCORE_REG_R8,
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XCORE_REG_R9,
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XCORE_REG_R10,
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XCORE_REG_R11,
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//> pseudo registers
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XCORE_REG_PC, // pc
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// internal thread registers
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// see The-XMOS-XS1-Architecture(X7879A).pdf
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XCORE_REG_SCP, // save pc
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XCORE_REG_SSR, // save status
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XCORE_REG_ET, // exception type
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XCORE_REG_ED, // exception data
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XCORE_REG_SED, // save exception data
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XCORE_REG_KEP, // kernel entry pointer
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XCORE_REG_KSP, // kernel stack pointer
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XCORE_REG_ID, // thread ID
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XCORE_REG_ENDING, // <-- mark the end of the list of registers
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} xcore_reg;
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//> XCore instruction
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typedef enum xcore_insn {
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XCORE_INS_INVALID = 0,
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XCORE_INS_ADD,
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XCORE_INS_ANDNOT,
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XCORE_INS_AND,
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XCORE_INS_ASHR,
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XCORE_INS_BAU,
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XCORE_INS_BITREV,
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XCORE_INS_BLA,
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XCORE_INS_BLAT,
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XCORE_INS_BL,
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XCORE_INS_BF,
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XCORE_INS_BT,
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XCORE_INS_BU,
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XCORE_INS_BRU,
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XCORE_INS_BYTEREV,
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XCORE_INS_CHKCT,
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XCORE_INS_CLRE,
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XCORE_INS_CLRPT,
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XCORE_INS_CLRSR,
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XCORE_INS_CLZ,
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XCORE_INS_CRC8,
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XCORE_INS_CRC32,
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XCORE_INS_DCALL,
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XCORE_INS_DENTSP,
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XCORE_INS_DGETREG,
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XCORE_INS_DIVS,
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XCORE_INS_DIVU,
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XCORE_INS_DRESTSP,
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XCORE_INS_DRET,
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XCORE_INS_ECALLF,
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XCORE_INS_ECALLT,
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XCORE_INS_EDU,
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XCORE_INS_EEF,
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XCORE_INS_EET,
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XCORE_INS_EEU,
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XCORE_INS_ENDIN,
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XCORE_INS_ENTSP,
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XCORE_INS_EQ,
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XCORE_INS_EXTDP,
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XCORE_INS_EXTSP,
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XCORE_INS_FREER,
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XCORE_INS_FREET,
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XCORE_INS_GETD,
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XCORE_INS_GET,
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XCORE_INS_GETN,
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XCORE_INS_GETR,
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XCORE_INS_GETSR,
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XCORE_INS_GETST,
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XCORE_INS_GETTS,
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XCORE_INS_INCT,
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XCORE_INS_INIT,
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XCORE_INS_INPW,
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XCORE_INS_INSHR,
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XCORE_INS_INT,
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XCORE_INS_IN,
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XCORE_INS_KCALL,
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XCORE_INS_KENTSP,
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XCORE_INS_KRESTSP,
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XCORE_INS_KRET,
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XCORE_INS_LADD,
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XCORE_INS_LD16S,
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XCORE_INS_LD8U,
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XCORE_INS_LDA16,
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XCORE_INS_LDAP,
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XCORE_INS_LDAW,
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XCORE_INS_LDC,
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XCORE_INS_LDW,
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XCORE_INS_LDIVU,
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XCORE_INS_LMUL,
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XCORE_INS_LSS,
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XCORE_INS_LSUB,
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XCORE_INS_LSU,
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XCORE_INS_MACCS,
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XCORE_INS_MACCU,
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XCORE_INS_MJOIN,
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XCORE_INS_MKMSK,
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XCORE_INS_MSYNC,
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XCORE_INS_MUL,
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XCORE_INS_NEG,
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XCORE_INS_NOT,
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XCORE_INS_OR,
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XCORE_INS_OUTCT,
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XCORE_INS_OUTPW,
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XCORE_INS_OUTSHR,
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XCORE_INS_OUTT,
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XCORE_INS_OUT,
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XCORE_INS_PEEK,
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XCORE_INS_REMS,
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XCORE_INS_REMU,
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XCORE_INS_RETSP,
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XCORE_INS_SETCLK,
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XCORE_INS_SET,
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XCORE_INS_SETC,
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XCORE_INS_SETD,
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XCORE_INS_SETEV,
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XCORE_INS_SETN,
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XCORE_INS_SETPSC,
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XCORE_INS_SETPT,
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XCORE_INS_SETRDY,
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XCORE_INS_SETSR,
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XCORE_INS_SETTW,
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XCORE_INS_SETV,
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XCORE_INS_SEXT,
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XCORE_INS_SHL,
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XCORE_INS_SHR,
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XCORE_INS_SSYNC,
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XCORE_INS_ST16,
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XCORE_INS_ST8,
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XCORE_INS_STW,
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XCORE_INS_SUB,
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XCORE_INS_SYNCR,
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XCORE_INS_TESTCT,
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XCORE_INS_TESTLCL,
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XCORE_INS_TESTWCT,
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XCORE_INS_TSETMR,
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XCORE_INS_START,
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XCORE_INS_WAITEF,
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XCORE_INS_WAITET,
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XCORE_INS_WAITEU,
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XCORE_INS_XOR,
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XCORE_INS_ZEXT,
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XCORE_INS_ENDING, // <-- mark the end of the list of instructions
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} xcore_insn;
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//> Group of XCore instructions
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typedef enum xcore_insn_group {
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XCORE_GRP_INVALID = 0, // = CS_GRP_INVALID
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//> Generic groups
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// all jump instructions (conditional+direct+indirect jumps)
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XCORE_GRP_JUMP, // = CS_GRP_JUMP
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XCORE_GRP_ENDING, // <-- mark the end of the list of groups
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} xcore_insn_group;
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#ifdef __cplusplus
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}
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#endif
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#endif
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