177 lines
7.3 KiB
C++
177 lines
7.3 KiB
C++
// Copyright 2015, ARM Limited
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// * Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// * Neither the name of ARM Limited nor the names of its contributors may be
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// used to endorse or promote products derived from this software without
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// specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
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// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#ifndef VIXL_A64_DISASM_A64_H
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#define VIXL_A64_DISASM_A64_H
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#include "vixl/globals.h"
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#include "vixl/utils.h"
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#include "vixl/a64/instructions-a64.h"
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#include "vixl/a64/decoder-a64.h"
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#include "vixl/a64/assembler-a64.h"
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namespace vixl {
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class Disassembler: public DecoderVisitor {
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public:
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Disassembler();
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Disassembler(char* text_buffer, int buffer_size);
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virtual ~Disassembler();
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char* GetOutput();
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// Declare all Visitor functions.
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#define DECLARE(A) virtual void Visit##A(const Instruction* instr);
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VISITOR_LIST(DECLARE)
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#undef DECLARE
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protected:
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virtual void ProcessOutput(const Instruction* instr);
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// Default output functions. The functions below implement a default way of
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// printing elements in the disassembly. A sub-class can override these to
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// customize the disassembly output.
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// Prints the name of a register.
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// TODO: This currently doesn't allow renaming of V registers.
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virtual void AppendRegisterNameToOutput(const Instruction* instr,
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const CPURegister& reg);
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// Prints a PC-relative offset. This is used for example when disassembling
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// branches to immediate offsets.
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virtual void AppendPCRelativeOffsetToOutput(const Instruction* instr,
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int64_t offset);
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// Prints an address, in the general case. It can be code or data. This is
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// used for example to print the target address of an ADR instruction.
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virtual void AppendCodeRelativeAddressToOutput(const Instruction* instr,
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const void* addr);
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// Prints the address of some code.
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// This is used for example to print the target address of a branch to an
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// immediate offset.
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// A sub-class can for example override this method to lookup the address and
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// print an appropriate name.
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virtual void AppendCodeRelativeCodeAddressToOutput(const Instruction* instr,
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const void* addr);
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// Prints the address of some data.
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// This is used for example to print the source address of a load literal
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// instruction.
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virtual void AppendCodeRelativeDataAddressToOutput(const Instruction* instr,
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const void* addr);
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// Same as the above, but for addresses that are not relative to the code
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// buffer. They are currently not used by VIXL.
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virtual void AppendAddressToOutput(const Instruction* instr,
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const void* addr);
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virtual void AppendCodeAddressToOutput(const Instruction* instr,
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const void* addr);
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virtual void AppendDataAddressToOutput(const Instruction* instr,
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const void* addr);
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public:
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// Get/Set the offset that should be added to code addresses when printing
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// code-relative addresses in the AppendCodeRelative<Type>AddressToOutput()
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// helpers.
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// Below is an example of how a branch immediate instruction in memory at
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// address 0xb010200 would disassemble with different offsets.
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// Base address | Disassembly
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// 0x0 | 0xb010200: b #+0xcc (addr 0xb0102cc)
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// 0x10000 | 0xb000200: b #+0xcc (addr 0xb0002cc)
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// 0xb010200 | 0x0: b #+0xcc (addr 0xcc)
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void MapCodeAddress(int64_t base_address, const Instruction* instr_address);
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int64_t CodeRelativeAddress(const void* instr);
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private:
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void Format(
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const Instruction* instr, const char* mnemonic, const char* format);
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void Substitute(const Instruction* instr, const char* string);
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int SubstituteField(const Instruction* instr, const char* format);
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int SubstituteRegisterField(const Instruction* instr, const char* format);
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int SubstituteImmediateField(const Instruction* instr, const char* format);
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int SubstituteLiteralField(const Instruction* instr, const char* format);
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int SubstituteBitfieldImmediateField(
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const Instruction* instr, const char* format);
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int SubstituteShiftField(const Instruction* instr, const char* format);
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int SubstituteExtendField(const Instruction* instr, const char* format);
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int SubstituteConditionField(const Instruction* instr, const char* format);
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int SubstitutePCRelAddressField(const Instruction* instr, const char* format);
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int SubstituteBranchTargetField(const Instruction* instr, const char* format);
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int SubstituteLSRegOffsetField(const Instruction* instr, const char* format);
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int SubstitutePrefetchField(const Instruction* instr, const char* format);
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int SubstituteBarrierField(const Instruction* instr, const char* format);
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int SubstituteSysOpField(const Instruction* instr, const char* format);
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int SubstituteCrField(const Instruction* instr, const char* format);
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bool RdIsZROrSP(const Instruction* instr) const {
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return (instr->Rd() == kZeroRegCode);
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}
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bool RnIsZROrSP(const Instruction* instr) const {
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return (instr->Rn() == kZeroRegCode);
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}
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bool RmIsZROrSP(const Instruction* instr) const {
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return (instr->Rm() == kZeroRegCode);
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}
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bool RaIsZROrSP(const Instruction* instr) const {
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return (instr->Ra() == kZeroRegCode);
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}
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bool IsMovzMovnImm(unsigned reg_size, uint64_t value);
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int64_t code_address_offset() const { return code_address_offset_; }
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protected:
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void ResetOutput();
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void AppendToOutput(const char* string, ...) PRINTF_CHECK(2, 3);
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void set_code_address_offset(int64_t code_address_offset) {
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code_address_offset_ = code_address_offset;
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}
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char* buffer_;
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uint32_t buffer_pos_;
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uint32_t buffer_size_;
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bool own_buffer_;
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int64_t code_address_offset_;
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};
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class PrintDisassembler: public Disassembler {
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public:
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explicit PrintDisassembler(FILE* stream) : stream_(stream) { }
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protected:
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virtual void ProcessOutput(const Instruction* instr);
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private:
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FILE *stream_;
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};
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} // namespace vixl
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#endif // VIXL_A64_DISASM_A64_H
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