622 lines
17 KiB
C++
622 lines
17 KiB
C++
// Copyright 2015, ARM Limited
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// * Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// * Neither the name of ARM Limited nor the names of its contributors may be
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// used to endorse or promote products derived from this software without
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// specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
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// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#include "vixl/a64/instructions-a64.h"
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#include "vixl/a64/assembler-a64.h"
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namespace vixl {
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// Floating-point infinity values.
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const float16 kFP16PositiveInfinity = 0x7c00;
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const float16 kFP16NegativeInfinity = 0xfc00;
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const float kFP32PositiveInfinity = rawbits_to_float(0x7f800000);
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const float kFP32NegativeInfinity = rawbits_to_float(0xff800000);
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const double kFP64PositiveInfinity =
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rawbits_to_double(UINT64_C(0x7ff0000000000000));
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const double kFP64NegativeInfinity =
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rawbits_to_double(UINT64_C(0xfff0000000000000));
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// The default NaN values (for FPCR.DN=1).
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const double kFP64DefaultNaN = rawbits_to_double(UINT64_C(0x7ff8000000000000));
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const float kFP32DefaultNaN = rawbits_to_float(0x7fc00000);
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const float16 kFP16DefaultNaN = 0x7e00;
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static uint64_t RotateRight(uint64_t value,
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unsigned int rotate,
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unsigned int width) {
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VIXL_ASSERT(width <= 64);
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rotate &= 63;
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return ((value & ((UINT64_C(1) << rotate) - 1)) <<
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(width - rotate)) | (value >> rotate);
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}
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static uint64_t RepeatBitsAcrossReg(unsigned reg_size,
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uint64_t value,
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unsigned width) {
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VIXL_ASSERT((width == 2) || (width == 4) || (width == 8) || (width == 16) ||
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(width == 32));
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VIXL_ASSERT((reg_size == kWRegSize) || (reg_size == kXRegSize));
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uint64_t result = value & ((UINT64_C(1) << width) - 1);
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for (unsigned i = width; i < reg_size; i *= 2) {
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result |= (result << i);
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}
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return result;
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}
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bool Instruction::IsLoad() const {
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if (Mask(LoadStoreAnyFMask) != LoadStoreAnyFixed) {
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return false;
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}
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if (Mask(LoadStorePairAnyFMask) == LoadStorePairAnyFixed) {
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return Mask(LoadStorePairLBit) != 0;
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} else {
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LoadStoreOp op = static_cast<LoadStoreOp>(Mask(LoadStoreMask));
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switch (op) {
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case LDRB_w:
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case LDRH_w:
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case LDR_w:
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case LDR_x:
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case LDRSB_w:
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case LDRSB_x:
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case LDRSH_w:
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case LDRSH_x:
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case LDRSW_x:
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case LDR_b:
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case LDR_h:
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case LDR_s:
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case LDR_d:
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case LDR_q: return true;
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default: return false;
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}
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}
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}
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bool Instruction::IsStore() const {
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if (Mask(LoadStoreAnyFMask) != LoadStoreAnyFixed) {
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return false;
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}
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if (Mask(LoadStorePairAnyFMask) == LoadStorePairAnyFixed) {
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return Mask(LoadStorePairLBit) == 0;
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} else {
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LoadStoreOp op = static_cast<LoadStoreOp>(Mask(LoadStoreMask));
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switch (op) {
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case STRB_w:
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case STRH_w:
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case STR_w:
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case STR_x:
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case STR_b:
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case STR_h:
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case STR_s:
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case STR_d:
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case STR_q: return true;
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default: return false;
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}
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}
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}
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// Logical immediates can't encode zero, so a return value of zero is used to
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// indicate a failure case. Specifically, where the constraints on imm_s are
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// not met.
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uint64_t Instruction::ImmLogical() const {
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unsigned reg_size = SixtyFourBits() ? kXRegSize : kWRegSize;
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int32_t n = BitN();
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int32_t imm_s = ImmSetBits();
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int32_t imm_r = ImmRotate();
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// An integer is constructed from the n, imm_s and imm_r bits according to
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// the following table:
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//
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// N imms immr size S R
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// 1 ssssss rrrrrr 64 UInt(ssssss) UInt(rrrrrr)
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// 0 0sssss xrrrrr 32 UInt(sssss) UInt(rrrrr)
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// 0 10ssss xxrrrr 16 UInt(ssss) UInt(rrrr)
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// 0 110sss xxxrrr 8 UInt(sss) UInt(rrr)
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// 0 1110ss xxxxrr 4 UInt(ss) UInt(rr)
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// 0 11110s xxxxxr 2 UInt(s) UInt(r)
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// (s bits must not be all set)
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//
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// A pattern is constructed of size bits, where the least significant S+1
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// bits are set. The pattern is rotated right by R, and repeated across a
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// 32 or 64-bit value, depending on destination register width.
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//
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if (n == 1) {
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if (imm_s == 0x3f) {
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return 0;
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}
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uint64_t bits = (UINT64_C(1) << (imm_s + 1)) - 1;
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return RotateRight(bits, imm_r, 64);
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} else {
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if ((imm_s >> 1) == 0x1f) {
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return 0;
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}
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for (int width = 0x20; width >= 0x2; width >>= 1) {
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if ((imm_s & width) == 0) {
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int mask = width - 1;
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if ((imm_s & mask) == mask) {
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return 0;
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}
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uint64_t bits = (UINT64_C(1) << ((imm_s & mask) + 1)) - 1;
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return RepeatBitsAcrossReg(reg_size,
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RotateRight(bits, imm_r & mask, width),
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width);
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}
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}
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}
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VIXL_UNREACHABLE();
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return 0;
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}
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uint32_t Instruction::ImmNEONabcdefgh() const {
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return ImmNEONabc() << 5 | ImmNEONdefgh();
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}
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float Instruction::Imm8ToFP32(uint32_t imm8) {
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// Imm8: abcdefgh (8 bits)
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// Single: aBbb.bbbc.defg.h000.0000.0000.0000.0000 (32 bits)
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// where B is b ^ 1
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uint32_t bits = imm8;
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uint32_t bit7 = (bits >> 7) & 0x1;
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uint32_t bit6 = (bits >> 6) & 0x1;
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uint32_t bit5_to_0 = bits & 0x3f;
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uint32_t result = (bit7 << 31) | ((32 - bit6) << 25) | (bit5_to_0 << 19);
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return rawbits_to_float(result);
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}
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float Instruction::ImmFP32() const {
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return Imm8ToFP32(ImmFP());
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}
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double Instruction::Imm8ToFP64(uint32_t imm8) {
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// Imm8: abcdefgh (8 bits)
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// Double: aBbb.bbbb.bbcd.efgh.0000.0000.0000.0000
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// 0000.0000.0000.0000.0000.0000.0000.0000 (64 bits)
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// where B is b ^ 1
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uint32_t bits = imm8;
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uint64_t bit7 = (bits >> 7) & 0x1;
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uint64_t bit6 = (bits >> 6) & 0x1;
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uint64_t bit5_to_0 = bits & 0x3f;
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uint64_t result = (bit7 << 63) | ((256 - bit6) << 54) | (bit5_to_0 << 48);
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return rawbits_to_double(result);
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}
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double Instruction::ImmFP64() const {
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return Imm8ToFP64(ImmFP());
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}
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float Instruction::ImmNEONFP32() const {
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return Imm8ToFP32(ImmNEONabcdefgh());
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}
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double Instruction::ImmNEONFP64() const {
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return Imm8ToFP64(ImmNEONabcdefgh());
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}
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unsigned CalcLSDataSize(LoadStoreOp op) {
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VIXL_ASSERT((LSSize_offset + LSSize_width) == (kInstructionSize * 8));
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unsigned size = static_cast<Instr>(op) >> LSSize_offset;
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if ((op & LSVector_mask) != 0) {
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// Vector register memory operations encode the access size in the "size"
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// and "opc" fields.
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if ((size == 0) && ((op & LSOpc_mask) >> LSOpc_offset) >= 2) {
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size = kQRegSizeInBytesLog2;
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}
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}
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return size;
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}
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unsigned CalcLSPairDataSize(LoadStorePairOp op) {
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VIXL_STATIC_ASSERT(kXRegSizeInBytes == kDRegSizeInBytes);
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VIXL_STATIC_ASSERT(kWRegSizeInBytes == kSRegSizeInBytes);
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switch (op) {
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case STP_q:
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case LDP_q: return kQRegSizeInBytesLog2;
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case STP_x:
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case LDP_x:
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case STP_d:
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case LDP_d: return kXRegSizeInBytesLog2;
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default: return kWRegSizeInBytesLog2;
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}
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}
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int Instruction::ImmBranchRangeBitwidth(ImmBranchType branch_type) {
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switch (branch_type) {
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case UncondBranchType:
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return ImmUncondBranch_width;
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case CondBranchType:
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return ImmCondBranch_width;
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case CompareBranchType:
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return ImmCmpBranch_width;
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case TestBranchType:
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return ImmTestBranch_width;
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default:
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VIXL_UNREACHABLE();
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return 0;
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}
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}
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int32_t Instruction::ImmBranchForwardRange(ImmBranchType branch_type) {
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int32_t encoded_max = 1 << (ImmBranchRangeBitwidth(branch_type) - 1);
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return encoded_max * kInstructionSize;
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}
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bool Instruction::IsValidImmPCOffset(ImmBranchType branch_type,
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int64_t offset) {
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return is_intn(ImmBranchRangeBitwidth(branch_type), offset);
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}
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const Instruction* Instruction::ImmPCOffsetTarget() const {
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const Instruction * base = this;
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ptrdiff_t offset;
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if (IsPCRelAddressing()) {
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// ADR and ADRP.
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offset = ImmPCRel();
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if (Mask(PCRelAddressingMask) == ADRP) {
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base = AlignDown(base, kPageSize);
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offset *= kPageSize;
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} else {
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VIXL_ASSERT(Mask(PCRelAddressingMask) == ADR);
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}
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} else {
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// All PC-relative branches.
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VIXL_ASSERT(BranchType() != UnknownBranchType);
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// Relative branch offsets are instruction-size-aligned.
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offset = ImmBranch() << kInstructionSizeLog2;
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}
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return base + offset;
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}
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int Instruction::ImmBranch() const {
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switch (BranchType()) {
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case CondBranchType: return ImmCondBranch();
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case UncondBranchType: return ImmUncondBranch();
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case CompareBranchType: return ImmCmpBranch();
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case TestBranchType: return ImmTestBranch();
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default: VIXL_UNREACHABLE();
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}
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return 0;
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}
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void Instruction::SetImmPCOffsetTarget(const Instruction* target) {
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if (IsPCRelAddressing()) {
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SetPCRelImmTarget(target);
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} else {
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SetBranchImmTarget(target);
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}
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}
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void Instruction::SetPCRelImmTarget(const Instruction* target) {
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ptrdiff_t imm21;
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if ((Mask(PCRelAddressingMask) == ADR)) {
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imm21 = target - this;
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} else {
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VIXL_ASSERT(Mask(PCRelAddressingMask) == ADRP);
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uintptr_t this_page = reinterpret_cast<uintptr_t>(this) / kPageSize;
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uintptr_t target_page = reinterpret_cast<uintptr_t>(target) / kPageSize;
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imm21 = target_page - this_page;
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}
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Instr imm = Assembler::ImmPCRelAddress(static_cast<int32_t>(imm21));
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SetInstructionBits(Mask(~ImmPCRel_mask) | imm);
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}
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void Instruction::SetBranchImmTarget(const Instruction* target) {
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VIXL_ASSERT(((target - this) & 3) == 0);
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Instr branch_imm = 0;
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uint32_t imm_mask = 0;
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int offset = static_cast<int>((target - this) >> kInstructionSizeLog2);
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switch (BranchType()) {
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case CondBranchType: {
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branch_imm = Assembler::ImmCondBranch(offset);
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imm_mask = ImmCondBranch_mask;
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break;
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}
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case UncondBranchType: {
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branch_imm = Assembler::ImmUncondBranch(offset);
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imm_mask = ImmUncondBranch_mask;
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break;
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}
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case CompareBranchType: {
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branch_imm = Assembler::ImmCmpBranch(offset);
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imm_mask = ImmCmpBranch_mask;
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break;
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}
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case TestBranchType: {
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branch_imm = Assembler::ImmTestBranch(offset);
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imm_mask = ImmTestBranch_mask;
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break;
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}
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default: VIXL_UNREACHABLE();
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}
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SetInstructionBits(Mask(~imm_mask) | branch_imm);
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}
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void Instruction::SetImmLLiteral(const Instruction* source) {
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VIXL_ASSERT(IsWordAligned(source));
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ptrdiff_t offset = (source - this) >> kLiteralEntrySizeLog2;
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Instr imm = Assembler::ImmLLiteral(static_cast<int>(offset));
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Instr mask = ImmLLiteral_mask;
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SetInstructionBits(Mask(~mask) | imm);
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}
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VectorFormat VectorFormatHalfWidth(const VectorFormat vform) {
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VIXL_ASSERT(vform == kFormat8H || vform == kFormat4S || vform == kFormat2D ||
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vform == kFormatH || vform == kFormatS || vform == kFormatD);
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switch (vform) {
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case kFormat8H: return kFormat8B;
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case kFormat4S: return kFormat4H;
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case kFormat2D: return kFormat2S;
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case kFormatH: return kFormatB;
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case kFormatS: return kFormatH;
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case kFormatD: return kFormatS;
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default: VIXL_UNREACHABLE(); return kFormatUndefined;
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}
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}
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VectorFormat VectorFormatDoubleWidth(const VectorFormat vform) {
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VIXL_ASSERT(vform == kFormat8B || vform == kFormat4H || vform == kFormat2S ||
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vform == kFormatB || vform == kFormatH || vform == kFormatS);
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switch (vform) {
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case kFormat8B: return kFormat8H;
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case kFormat4H: return kFormat4S;
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case kFormat2S: return kFormat2D;
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case kFormatB: return kFormatH;
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case kFormatH: return kFormatS;
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case kFormatS: return kFormatD;
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default: VIXL_UNREACHABLE(); return kFormatUndefined;
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}
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}
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VectorFormat VectorFormatFillQ(const VectorFormat vform) {
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switch (vform) {
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case kFormatB:
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case kFormat8B:
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case kFormat16B: return kFormat16B;
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case kFormatH:
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case kFormat4H:
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case kFormat8H: return kFormat8H;
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case kFormatS:
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case kFormat2S:
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case kFormat4S: return kFormat4S;
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case kFormatD:
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case kFormat1D:
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case kFormat2D: return kFormat2D;
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default: VIXL_UNREACHABLE(); return kFormatUndefined;
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}
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}
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VectorFormat VectorFormatHalfWidthDoubleLanes(const VectorFormat vform) {
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switch (vform) {
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case kFormat4H: return kFormat8B;
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case kFormat8H: return kFormat16B;
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case kFormat2S: return kFormat4H;
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case kFormat4S: return kFormat8H;
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case kFormat1D: return kFormat2S;
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case kFormat2D: return kFormat4S;
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default: VIXL_UNREACHABLE(); return kFormatUndefined;
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}
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}
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VectorFormat VectorFormatDoubleLanes(const VectorFormat vform) {
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VIXL_ASSERT(vform == kFormat8B || vform == kFormat4H || vform == kFormat2S);
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switch (vform) {
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case kFormat8B: return kFormat16B;
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case kFormat4H: return kFormat8H;
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case kFormat2S: return kFormat4S;
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default: VIXL_UNREACHABLE(); return kFormatUndefined;
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}
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}
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VectorFormat VectorFormatHalfLanes(const VectorFormat vform) {
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VIXL_ASSERT(vform == kFormat16B || vform == kFormat8H || vform == kFormat4S);
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switch (vform) {
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case kFormat16B: return kFormat8B;
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case kFormat8H: return kFormat4H;
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case kFormat4S: return kFormat2S;
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default: VIXL_UNREACHABLE(); return kFormatUndefined;
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}
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}
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VectorFormat ScalarFormatFromLaneSize(int laneSize) {
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switch (laneSize) {
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case 8: return kFormatB;
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case 16: return kFormatH;
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case 32: return kFormatS;
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case 64: return kFormatD;
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default: VIXL_UNREACHABLE(); return kFormatUndefined;
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}
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}
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unsigned RegisterSizeInBitsFromFormat(VectorFormat vform) {
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VIXL_ASSERT(vform != kFormatUndefined);
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switch (vform) {
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case kFormatB: return kBRegSize;
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case kFormatH: return kHRegSize;
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case kFormatS: return kSRegSize;
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case kFormatD: return kDRegSize;
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case kFormat8B:
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case kFormat4H:
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case kFormat2S:
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case kFormat1D: return kDRegSize;
|
|
default: return kQRegSize;
|
|
}
|
|
}
|
|
|
|
|
|
unsigned RegisterSizeInBytesFromFormat(VectorFormat vform) {
|
|
return RegisterSizeInBitsFromFormat(vform) / 8;
|
|
}
|
|
|
|
|
|
unsigned LaneSizeInBitsFromFormat(VectorFormat vform) {
|
|
VIXL_ASSERT(vform != kFormatUndefined);
|
|
switch (vform) {
|
|
case kFormatB:
|
|
case kFormat8B:
|
|
case kFormat16B: return 8;
|
|
case kFormatH:
|
|
case kFormat4H:
|
|
case kFormat8H: return 16;
|
|
case kFormatS:
|
|
case kFormat2S:
|
|
case kFormat4S: return 32;
|
|
case kFormatD:
|
|
case kFormat1D:
|
|
case kFormat2D: return 64;
|
|
default: VIXL_UNREACHABLE(); return 0;
|
|
}
|
|
}
|
|
|
|
|
|
int LaneSizeInBytesFromFormat(VectorFormat vform) {
|
|
return LaneSizeInBitsFromFormat(vform) / 8;
|
|
}
|
|
|
|
|
|
int LaneSizeInBytesLog2FromFormat(VectorFormat vform) {
|
|
VIXL_ASSERT(vform != kFormatUndefined);
|
|
switch (vform) {
|
|
case kFormatB:
|
|
case kFormat8B:
|
|
case kFormat16B: return 0;
|
|
case kFormatH:
|
|
case kFormat4H:
|
|
case kFormat8H: return 1;
|
|
case kFormatS:
|
|
case kFormat2S:
|
|
case kFormat4S: return 2;
|
|
case kFormatD:
|
|
case kFormat1D:
|
|
case kFormat2D: return 3;
|
|
default: VIXL_UNREACHABLE(); return 0;
|
|
}
|
|
}
|
|
|
|
|
|
int LaneCountFromFormat(VectorFormat vform) {
|
|
VIXL_ASSERT(vform != kFormatUndefined);
|
|
switch (vform) {
|
|
case kFormat16B: return 16;
|
|
case kFormat8B:
|
|
case kFormat8H: return 8;
|
|
case kFormat4H:
|
|
case kFormat4S: return 4;
|
|
case kFormat2S:
|
|
case kFormat2D: return 2;
|
|
case kFormat1D:
|
|
case kFormatB:
|
|
case kFormatH:
|
|
case kFormatS:
|
|
case kFormatD: return 1;
|
|
default: VIXL_UNREACHABLE(); return 0;
|
|
}
|
|
}
|
|
|
|
|
|
int MaxLaneCountFromFormat(VectorFormat vform) {
|
|
VIXL_ASSERT(vform != kFormatUndefined);
|
|
switch (vform) {
|
|
case kFormatB:
|
|
case kFormat8B:
|
|
case kFormat16B: return 16;
|
|
case kFormatH:
|
|
case kFormat4H:
|
|
case kFormat8H: return 8;
|
|
case kFormatS:
|
|
case kFormat2S:
|
|
case kFormat4S: return 4;
|
|
case kFormatD:
|
|
case kFormat1D:
|
|
case kFormat2D: return 2;
|
|
default: VIXL_UNREACHABLE(); return 0;
|
|
}
|
|
}
|
|
|
|
|
|
// Does 'vform' indicate a vector format or a scalar format?
|
|
bool IsVectorFormat(VectorFormat vform) {
|
|
VIXL_ASSERT(vform != kFormatUndefined);
|
|
switch (vform) {
|
|
case kFormatB:
|
|
case kFormatH:
|
|
case kFormatS:
|
|
case kFormatD: return false;
|
|
default: return true;
|
|
}
|
|
}
|
|
|
|
|
|
int64_t MaxIntFromFormat(VectorFormat vform) {
|
|
return INT64_MAX >> (64 - LaneSizeInBitsFromFormat(vform));
|
|
}
|
|
|
|
|
|
int64_t MinIntFromFormat(VectorFormat vform) {
|
|
return INT64_MIN >> (64 - LaneSizeInBitsFromFormat(vform));
|
|
}
|
|
|
|
|
|
uint64_t MaxUintFromFormat(VectorFormat vform) {
|
|
return UINT64_MAX >> (64 - LaneSizeInBitsFromFormat(vform));
|
|
}
|
|
} // namespace vixl
|
|
|