263 lines
8.3 KiB
C
263 lines
8.3 KiB
C
/*
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* ARM SBSA Reference Platform emulation-based PCI
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*
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* Copyright (c) 2018 Linaro Limited
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* Copyright (c) 2023 Samuel Lord
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* Written by Hongbo Zhang <hongbo.zhang@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "qapi/error.h"
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#include "qemu/error-report.h"
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#include "qemu/units.h"
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#include "sysemu/device_tree.h"
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#include "sysemu/numa.h"
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#include "sysemu/runstate.h"
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#include "sysemu/sysemu.h"
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#include "exec/address-spaces.h"
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#include "exec/hwaddr.h"
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#include "kvm_arm.h"
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#include "hw/arm/boot.h"
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#include "hw/block/flash.h"
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#include "hw/boards.h"
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#include "hw/ide/internal.h"
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#include "hw/ide/ahci_internal.h"
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#include "hw/intc/arm_gicv3_common.h"
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#include "hw/loader.h"
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#include "hw/pci-host/gpex.h"
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#include "hw/qdev-properties.h"
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#include "hw/usb.h"
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#include "hw/char/pl011.h"
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#include "net/net.h"
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#define RAMLIMIT_GB 8192
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#define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB)
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#define NUM_IRQS 256
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#define NUM_SMMU_IRQS 4
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#define NUM_SATA_PORTS 6
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#define VIRTUAL_PMU_IRQ 7
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#define ARCH_GIC_MAINT_IRQ 9
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#define ARCH_TIMER_VIRT_IRQ 11
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#define ARCH_TIMER_S_EL1_IRQ 13
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#define ARCH_TIMER_NS_EL1_IRQ 14
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#define ARCH_TIMER_NS_EL2_IRQ 10
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enum {
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SBSA_FLASH,
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SBSA_MEM,
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SBSA_CPUPERIPHS,
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SBSA_GIC_DIST,
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SBSA_GIC_REDIST,
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SBSA_SMMU,
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SBSA_UART,
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SBSA_RTC,
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SBSA_PCIE,
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SBSA_PCIE_MMIO,
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SBSA_PCIE_MMIO_HIGH,
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SBSA_PCIE_PIO,
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SBSA_PCIE_ECAM,
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SBSA_GPIO,
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SBSA_SECURE_UART,
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SBSA_SECURE_UART_MM,
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SBSA_SECURE_MEM,
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SBSA_AHCI,
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SBSA_EHCI,
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};
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typedef struct MemMapEntry {
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hwaddr base;
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hwaddr size;
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} MemMapEntry;
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typedef struct {
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MachineState parent;
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struct arm_boot_info bootinfo;
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int smp_cpus;
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void *fdt;
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int fdt_size;
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int psci_conduit;
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DeviceState *gic;
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PFlashCFI01 *flash[2];
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} SBSAMachineState;
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#define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref")
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#define SBSA_MACHINE(obj) \
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OBJECT_CHECK(SBSAMachineState, (obj), TYPE_SBSA_MACHINE)
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static const MemMapEntry sbsa_ref_memmap[] = {
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/* 512M boot ROM */
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[SBSA_FLASH] = { 0, 0x20000000 },
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/* 512M secure memory */
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[SBSA_SECURE_MEM] = { 0x20000000, 0x20000000 },
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/* Space reserved for CPU peripheral devices */
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[SBSA_CPUPERIPHS] = { 0x40000000, 0x00040000 },
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[SBSA_GIC_DIST] = { 0x40060000, 0x00010000 },
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[SBSA_GIC_REDIST] = { 0x40080000, 0x04000000 },
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[SBSA_UART] = { 0x60000000, 0x00001000 },
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[SBSA_RTC] = { 0x60010000, 0x00001000 },
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[SBSA_GPIO] = { 0x60020000, 0x00001000 },
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[SBSA_SECURE_UART] = { 0x60030000, 0x00001000 },
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[SBSA_SECURE_UART_MM] = { 0x60040000, 0x00001000 },
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[SBSA_SMMU] = { 0x60050000, 0x00020000 },
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/* Space here reserved for more SMMUs */
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[SBSA_AHCI] = { 0x60100000, 0x00010000 },
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[SBSA_EHCI] = { 0x60110000, 0x00010000 },
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/* Space here reserved for other devices */
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[SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 },
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/* 32-bit address PCIE MMIO space */
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[SBSA_PCIE_MMIO] = { 0x80000000, 0x70000000 },
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/* 256M PCIE ECAM space */
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[SBSA_PCIE_ECAM] = { 0xf0000000, 0x10000000 },
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/* ~1TB PCIE MMIO space (4GB to 1024GB boundary) */
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[SBSA_PCIE_MMIO_HIGH] = { 0x100000000ULL, 0xFF00000000ULL },
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[SBSA_MEM] = { 0x10000000000ULL, RAMLIMIT_BYTES },
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};
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static const int sbsa_ref_irqmap[] = {
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[SBSA_UART] = 1,
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[SBSA_RTC] = 2,
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[SBSA_PCIE] = 3, /* ... to 6 */
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[SBSA_GPIO] = 7,
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[SBSA_SECURE_UART] = 8,
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[SBSA_SECURE_UART_MM] = 9,
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[SBSA_AHCI] = 10,
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[SBSA_EHCI] = 11,
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};
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static void create_ahci(const SBSAMachineState *sms)
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{
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hwaddr base = sbsa_ref_memmap[SBSA_AHCI].base;
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int irq = sbsa_ref_irqmap[SBSA_AHCI];
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DeviceState *dev;
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DriveInfo *hd[NUM_SATA_PORTS];
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SysbusAHCIState *sysahci;
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AHCIState *ahci;
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int i;
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dev = qdev_new("sysbus-ahci");
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qdev_prop_set_uint32(dev, "num-ports", NUM_SATA_PORTS);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq));
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sysahci = SYSBUS_AHCI(dev);
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ahci = &sysahci->ahci;
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ide_drive_get(hd, ARRAY_SIZE(hd));
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for (i = 0; i < ahci->ports; i++) {
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if (hd[i] == NULL) {
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continue;
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}
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ide_create_drive(&ahci->dev[i].port, 0, hd[i]);
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}
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}
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static void create_ehci(const SBSAMachineState *sms)
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{
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hwaddr base = sbsa_ref_memmap[SBSA_EHCI].base;
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int irq = sbsa_ref_irqmap[SBSA_EHCI];
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sysbus_create_simple("platform-ehci-usb", base,
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qdev_get_gpio_in(sms->gic, irq));
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}
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static void create_smmu(const SBSAMachineState *sms, PCIBus *bus)
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{
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hwaddr base = sbsa_ref_memmap[SBSA_SMMU].base;
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int irq = sbsa_ref_irqmap[SBSA_SMMU];
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DeviceState *dev;
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int i;
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dev = qdev_new("arm-smmuv3");
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object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus),
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&error_abort);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
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for (i = 0; i < NUM_SMMU_IRQS; i++) {
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
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qdev_get_gpio_in(sms->gic, irq + 1));
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}
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}
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static void create_pcie(SBSAMachineState *sms)
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{
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hwaddr base_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].base;
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hwaddr size_ecam = sbsa_ref_memmap[SBSA_PCIE_ECAM].size;
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hwaddr base_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].base;
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hwaddr size_mmio = sbsa_ref_memmap[SBSA_PCIE_MMIO].size;
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hwaddr base_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].base;
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hwaddr size_mmio_high = sbsa_ref_memmap[SBSA_PCIE_MMIO_HIGH].size;
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hwaddr base_pio = sbsa_ref_memmap[SBSA_PCIE_PIO].base;
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int irq = sbsa_ref_irqmap[SBSA_PCIE];
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MemoryRegion *mmio_alias, *mmio_alias_high, *mmio_reg;
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MemoryRegion *ecam_alias, *ecam_reg;
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DeviceState *dev;
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PCIHostState *pci;
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int i;
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dev = qdev_new(TYPE_GPEX_HOST);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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/* Map ECAM space */
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ecam_alias = g_new0(MemoryRegion, 1);
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ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
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memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
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ecam_reg, 0, size_ecam);
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memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
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/* Map the MMIO space */
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mmio_alias = g_new0(MemoryRegion, 1);
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mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
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memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
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mmio_reg, base_mmio, size_mmio);
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memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
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/* Map the MMIO_HIGH space */
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mmio_alias_high = g_new0(MemoryRegion, 1);
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memory_region_init_alias(mmio_alias_high, OBJECT(dev), "pcie-mmio-high",
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mmio_reg, base_mmio_high, size_mmio_high);
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memory_region_add_subregion(get_system_memory(), base_mmio_high,
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mmio_alias_high);
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/* Map IO port space */
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
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for (i = 0; i < GPEX_NUM_IRQS; i++) {
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
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qdev_get_gpio_in(sms->gic, irq + 1));
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gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
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}
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pci = PCI_HOST_BRIDGE(dev);
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if (pci->bus) {
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for (i = 0; i < nb_nics; i++) {
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NICInfo *nd = &nd_table[i];
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if (!nd->model) {
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nd->model = g_strdup("e1000e");
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}
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pci_nic_init_nofail(nd, pci->bus, nd->model, NULL);
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}
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}
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pci_create_simple(pci->bus, -1, "VGA");
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create_smmu(sms, pci->bus);
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}
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