516 lines
15 KiB
C
516 lines
15 KiB
C
/*
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* QEMU lowRISC Ibex UART device
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*
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* Copyright (c) 2020 Western Digital
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*
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* For details check the documentation here:
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* https://docs.opentitan.org/hw/ip/uart/doc/
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/char/ibex_uart.h"
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#include "hw/irq.h"
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#include "hw/qdev-clock.h"
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#include "hw/qdev-properties.h"
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#include "migration/vmstate.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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static void ibex_uart_update_irqs(IbexUartState *s)
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{
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if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_TX_WATERMARK_MASK) {
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qemu_set_irq(s->tx_watermark, 1);
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} else {
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qemu_set_irq(s->tx_watermark, 0);
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}
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if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_RX_WATERMARK_MASK) {
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qemu_set_irq(s->rx_watermark, 1);
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} else {
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qemu_set_irq(s->rx_watermark, 0);
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}
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if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_TX_EMPTY_MASK) {
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qemu_set_irq(s->tx_empty, 1);
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} else {
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qemu_set_irq(s->tx_empty, 0);
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}
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if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_RX_OVERFLOW_MASK) {
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qemu_set_irq(s->rx_overflow, 1);
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} else {
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qemu_set_irq(s->rx_overflow, 0);
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}
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}
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static int ibex_uart_can_receive(void *opaque)
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{
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IbexUartState *s = opaque;
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if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
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return 1;
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}
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return 0;
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}
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static void ibex_uart_receive(void *opaque, const uint8_t *buf, int size)
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{
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IbexUartState *s = opaque;
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uint8_t rx_fifo_level = (s->uart_fifo_ctrl & R_FIFO_CTRL_RXILVL_MASK)
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>> R_FIFO_CTRL_RXILVL_SHIFT;
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s->uart_rdata = *buf;
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s->uart_status &= ~R_STATUS_RXIDLE_MASK;
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s->uart_status &= ~R_STATUS_RXEMPTY_MASK;
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if (size > rx_fifo_level) {
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s->uart_intr_state |= R_INTR_STATE_RX_WATERMARK_MASK;
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}
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ibex_uart_update_irqs(s);
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}
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static gboolean ibex_uart_xmit(GIOChannel *chan, GIOCondition cond,
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void *opaque)
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{
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IbexUartState *s = opaque;
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uint8_t tx_fifo_level = (s->uart_fifo_ctrl & R_FIFO_CTRL_TXILVL_MASK)
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>> R_FIFO_CTRL_TXILVL_SHIFT;
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int ret;
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/* instant drain the fifo when there's no back-end */
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if (!qemu_chr_fe_backend_connected(&s->chr)) {
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s->tx_level = 0;
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return FALSE;
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}
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if (!s->tx_level) {
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s->uart_status &= ~R_STATUS_TXFULL_MASK;
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s->uart_status |= R_STATUS_TXEMPTY_MASK;
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s->uart_intr_state |= R_INTR_STATE_TX_EMPTY_MASK;
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s->uart_intr_state &= ~R_INTR_STATE_TX_WATERMARK_MASK;
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ibex_uart_update_irqs(s);
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return FALSE;
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}
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ret = qemu_chr_fe_write(&s->chr, s->tx_fifo, s->tx_level);
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if (ret >= 0) {
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s->tx_level -= ret;
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memmove(s->tx_fifo, s->tx_fifo + ret, s->tx_level);
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}
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if (s->tx_level) {
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guint r = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
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ibex_uart_xmit, s);
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if (!r) {
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s->tx_level = 0;
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return FALSE;
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}
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}
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/* Clear the TX Full bit */
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if (s->tx_level != IBEX_UART_TX_FIFO_SIZE) {
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s->uart_status &= ~R_STATUS_TXFULL_MASK;
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}
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/* Disable the TX_WATERMARK IRQ */
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if (s->tx_level < tx_fifo_level) {
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s->uart_intr_state &= ~R_INTR_STATE_TX_WATERMARK_MASK;
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}
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/* Set TX empty */
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if (s->tx_level == 0) {
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s->uart_status |= R_STATUS_TXEMPTY_MASK;
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s->uart_intr_state |= R_INTR_STATE_TX_EMPTY_MASK;
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}
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ibex_uart_update_irqs(s);
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return FALSE;
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}
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static void uart_write_tx_fifo(IbexUartState *s, const uint8_t *buf,
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int size)
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{
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uint64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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uint8_t tx_fifo_level = (s->uart_fifo_ctrl & R_FIFO_CTRL_TXILVL_MASK)
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>> R_FIFO_CTRL_TXILVL_SHIFT;
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if (size > IBEX_UART_TX_FIFO_SIZE - s->tx_level) {
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size = IBEX_UART_TX_FIFO_SIZE - s->tx_level;
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qemu_log_mask(LOG_GUEST_ERROR, "ibex_uart: TX FIFO overflow");
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}
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memcpy(s->tx_fifo + s->tx_level, buf, size);
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s->tx_level += size;
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if (s->tx_level > 0) {
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s->uart_status &= ~R_STATUS_TXEMPTY_MASK;
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}
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if (s->tx_level >= tx_fifo_level) {
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s->uart_intr_state |= R_INTR_STATE_TX_WATERMARK_MASK;
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ibex_uart_update_irqs(s);
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}
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if (s->tx_level == IBEX_UART_TX_FIFO_SIZE) {
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s->uart_status |= R_STATUS_TXFULL_MASK;
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}
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timer_mod(s->fifo_trigger_handle, current_time +
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(s->char_tx_time * 4));
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}
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static void ibex_uart_reset(DeviceState *dev)
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{
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IbexUartState *s = IBEX_UART(dev);
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s->uart_intr_state = 0x00000000;
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s->uart_intr_state = 0x00000000;
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s->uart_intr_enable = 0x00000000;
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s->uart_ctrl = 0x00000000;
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s->uart_status = 0x0000003c;
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s->uart_rdata = 0x00000000;
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s->uart_fifo_ctrl = 0x00000000;
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s->uart_fifo_status = 0x00000000;
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s->uart_ovrd = 0x00000000;
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s->uart_val = 0x00000000;
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s->uart_timeout_ctrl = 0x00000000;
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s->tx_level = 0;
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s->char_tx_time = (NANOSECONDS_PER_SECOND / 230400) * 10;
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ibex_uart_update_irqs(s);
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}
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static uint64_t ibex_uart_get_baud(IbexUartState *s)
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{
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uint64_t baud;
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baud = ((s->uart_ctrl & R_CTRL_NCO_MASK) >> 16);
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baud *= clock_get_hz(s->f_clk);
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baud >>= 20;
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return baud;
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}
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static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
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unsigned int size)
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{
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IbexUartState *s = opaque;
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uint64_t retvalue = 0;
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switch (addr >> 2) {
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case R_INTR_STATE:
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retvalue = s->uart_intr_state;
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break;
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case R_INTR_ENABLE:
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retvalue = s->uart_intr_enable;
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break;
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case R_INTR_TEST:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: wdata is write only\n", __func__);
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break;
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case R_CTRL:
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retvalue = s->uart_ctrl;
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break;
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case R_STATUS:
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retvalue = s->uart_status;
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break;
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case R_RDATA:
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retvalue = s->uart_rdata;
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if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
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qemu_chr_fe_accept_input(&s->chr);
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s->uart_status |= R_STATUS_RXIDLE_MASK;
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s->uart_status |= R_STATUS_RXEMPTY_MASK;
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}
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break;
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case R_WDATA:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: wdata is write only\n", __func__);
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break;
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case R_FIFO_CTRL:
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retvalue = s->uart_fifo_ctrl;
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break;
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case R_FIFO_STATUS:
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retvalue = s->uart_fifo_status;
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retvalue |= s->tx_level & 0x1F;
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qemu_log_mask(LOG_UNIMP,
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"%s: RX fifos are not supported\n", __func__);
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break;
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case R_OVRD:
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retvalue = s->uart_ovrd;
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qemu_log_mask(LOG_UNIMP,
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"%s: ovrd is not supported\n", __func__);
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break;
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case R_VAL:
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retvalue = s->uart_val;
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qemu_log_mask(LOG_UNIMP,
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"%s: val is not supported\n", __func__);
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break;
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case R_TIMEOUT_CTRL:
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retvalue = s->uart_timeout_ctrl;
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qemu_log_mask(LOG_UNIMP,
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"%s: timeout_ctrl is not supported\n", __func__);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
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return 0;
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}
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return retvalue;
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}
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static void ibex_uart_write(void *opaque, hwaddr addr,
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uint64_t val64, unsigned int size)
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{
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IbexUartState *s = opaque;
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uint32_t value = val64;
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switch (addr >> 2) {
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case R_INTR_STATE:
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/* Write 1 clear */
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s->uart_intr_state &= ~value;
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ibex_uart_update_irqs(s);
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break;
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case R_INTR_ENABLE:
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s->uart_intr_enable = value;
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ibex_uart_update_irqs(s);
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break;
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case R_INTR_TEST:
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s->uart_intr_state |= value;
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ibex_uart_update_irqs(s);
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break;
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case R_CTRL:
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s->uart_ctrl = value;
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if (value & R_CTRL_NF_MASK) {
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qemu_log_mask(LOG_UNIMP,
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"%s: UART_CTRL_NF is not supported\n", __func__);
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}
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if (value & R_CTRL_SLPBK_MASK) {
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qemu_log_mask(LOG_UNIMP,
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"%s: UART_CTRL_SLPBK is not supported\n", __func__);
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}
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if (value & R_CTRL_LLPBK_MASK) {
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qemu_log_mask(LOG_UNIMP,
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"%s: UART_CTRL_LLPBK is not supported\n", __func__);
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}
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if (value & R_CTRL_PARITY_EN_MASK) {
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qemu_log_mask(LOG_UNIMP,
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"%s: UART_CTRL_PARITY_EN is not supported\n",
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__func__);
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}
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if (value & R_CTRL_PARITY_ODD_MASK) {
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qemu_log_mask(LOG_UNIMP,
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"%s: UART_CTRL_PARITY_ODD is not supported\n",
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__func__);
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}
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if (value & R_CTRL_RXBLVL_MASK) {
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qemu_log_mask(LOG_UNIMP,
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"%s: UART_CTRL_RXBLVL is not supported\n", __func__);
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}
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if (value & R_CTRL_NCO_MASK) {
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uint64_t baud = ibex_uart_get_baud(s);
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s->char_tx_time = (NANOSECONDS_PER_SECOND / baud) * 10;
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}
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break;
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case R_STATUS:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: status is read only\n", __func__);
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break;
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case R_RDATA:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: rdata is read only\n", __func__);
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break;
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case R_WDATA:
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uart_write_tx_fifo(s, (uint8_t *) &value, 1);
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break;
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case R_FIFO_CTRL:
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s->uart_fifo_ctrl = value;
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if (value & R_FIFO_CTRL_RXRST_MASK) {
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qemu_log_mask(LOG_UNIMP,
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"%s: RX fifos are not supported\n", __func__);
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}
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if (value & R_FIFO_CTRL_TXRST_MASK) {
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s->tx_level = 0;
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}
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break;
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case R_FIFO_STATUS:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: fifo_status is read only\n", __func__);
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break;
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case R_OVRD:
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s->uart_ovrd = value;
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qemu_log_mask(LOG_UNIMP,
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"%s: ovrd is not supported\n", __func__);
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break;
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case R_VAL:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: val is read only\n", __func__);
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break;
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case R_TIMEOUT_CTRL:
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s->uart_timeout_ctrl = value;
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qemu_log_mask(LOG_UNIMP,
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"%s: timeout_ctrl is not supported\n", __func__);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
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}
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}
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static void ibex_uart_clk_update(void *opaque)
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{
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IbexUartState *s = opaque;
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/* recompute uart's speed on clock change */
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uint64_t baud = ibex_uart_get_baud(s);
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s->char_tx_time = (NANOSECONDS_PER_SECOND / baud) * 10;
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}
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static void fifo_trigger_update(void *opaque)
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{
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IbexUartState *s = opaque;
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if (s->uart_ctrl & R_CTRL_TX_ENABLE_MASK) {
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ibex_uart_xmit(NULL, G_IO_OUT, s);
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}
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}
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static const MemoryRegionOps ibex_uart_ops = {
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.read = ibex_uart_read,
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.write = ibex_uart_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.impl.min_access_size = 4,
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.impl.max_access_size = 4,
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};
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static int ibex_uart_post_load(void *opaque, int version_id)
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{
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IbexUartState *s = opaque;
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ibex_uart_update_irqs(s);
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return 0;
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}
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static const VMStateDescription vmstate_ibex_uart = {
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.name = TYPE_IBEX_UART,
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.version_id = 1,
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.minimum_version_id = 1,
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.post_load = ibex_uart_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_UINT8_ARRAY(tx_fifo, IbexUartState,
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IBEX_UART_TX_FIFO_SIZE),
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VMSTATE_UINT32(tx_level, IbexUartState),
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VMSTATE_UINT64(char_tx_time, IbexUartState),
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VMSTATE_TIMER_PTR(fifo_trigger_handle, IbexUartState),
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VMSTATE_UINT32(uart_intr_state, IbexUartState),
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VMSTATE_UINT32(uart_intr_enable, IbexUartState),
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VMSTATE_UINT32(uart_ctrl, IbexUartState),
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VMSTATE_UINT32(uart_status, IbexUartState),
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VMSTATE_UINT32(uart_rdata, IbexUartState),
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VMSTATE_UINT32(uart_fifo_ctrl, IbexUartState),
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VMSTATE_UINT32(uart_fifo_status, IbexUartState),
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VMSTATE_UINT32(uart_ovrd, IbexUartState),
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VMSTATE_UINT32(uart_val, IbexUartState),
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VMSTATE_UINT32(uart_timeout_ctrl, IbexUartState),
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VMSTATE_END_OF_LIST()
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}
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};
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static Property ibex_uart_properties[] = {
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DEFINE_PROP_CHR("chardev", IbexUartState, chr),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void ibex_uart_init(Object *obj)
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{
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IbexUartState *s = IBEX_UART(obj);
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s->f_clk = qdev_init_clock_in(DEVICE(obj), "f_clock",
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ibex_uart_clk_update, s);
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clock_set_hz(s->f_clk, IBEX_UART_CLOCK);
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sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->tx_watermark);
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sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->rx_watermark);
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sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->tx_empty);
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sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->rx_overflow);
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memory_region_init_io(&s->mmio, obj, &ibex_uart_ops, s,
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TYPE_IBEX_UART, 0x400);
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sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
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}
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static void ibex_uart_realize(DeviceState *dev, Error **errp)
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{
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IbexUartState *s = IBEX_UART(dev);
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|
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s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,
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fifo_trigger_update, s);
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|
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qemu_chr_fe_set_handlers(&s->chr, ibex_uart_can_receive,
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ibex_uart_receive, NULL, NULL,
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s, NULL, true);
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}
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|
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static void ibex_uart_class_init(ObjectClass *klass, void *data)
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|
{
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DeviceClass *dc = DEVICE_CLASS(klass);
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|
|
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dc->reset = ibex_uart_reset;
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dc->realize = ibex_uart_realize;
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dc->vmsd = &vmstate_ibex_uart;
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device_class_set_props(dc, ibex_uart_properties);
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}
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|
|
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static const TypeInfo ibex_uart_info = {
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.name = TYPE_IBEX_UART,
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|
.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(IbexUartState),
|
|
.instance_init = ibex_uart_init,
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|
.class_init = ibex_uart_class_init,
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|
};
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|
|
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static void ibex_uart_register_types(void)
|
|
{
|
|
type_register_static(&ibex_uart_info);
|
|
}
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|
|
|
type_init(ibex_uart_register_types)
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