569 lines
14 KiB
C
569 lines
14 KiB
C
/*
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* Arm PrimeCell PL110 Color LCD Controller
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*
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* Copyright (c) 2005-2009 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licensed under the GNU LGPL
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*/
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#include "qemu/osdep.h"
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#include "hw/irq.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "ui/console.h"
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#include "framebuffer.h"
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#include "ui/pixel_ops.h"
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#include "qemu/timer.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#define PL110_CR_EN 0x001
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#define PL110_CR_BGR 0x100
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#define PL110_CR_BEBO 0x200
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#define PL110_CR_BEPO 0x400
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#define PL110_CR_PWR 0x800
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#define PL110_IE_NB 0x004
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#define PL110_IE_VC 0x008
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enum pl110_bppmode
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{
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BPP_1,
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BPP_2,
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BPP_4,
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BPP_8,
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BPP_16,
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BPP_32,
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BPP_16_565, /* PL111 only */
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BPP_12 /* PL111 only */
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};
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/* The Versatile/PB uses a slightly modified PL110 controller. */
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enum pl110_version
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{
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PL110,
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PL110_VERSATILE,
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PL111
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};
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#define TYPE_PL110 "pl110"
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#define PL110(obj) OBJECT_CHECK(PL110State, (obj), TYPE_PL110)
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typedef struct PL110State {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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MemoryRegionSection fbsection;
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QemuConsole *con;
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QEMUTimer *vblank_timer;
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int version;
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uint32_t timing[4];
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uint32_t cr;
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uint32_t upbase;
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uint32_t lpbase;
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uint32_t int_status;
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uint32_t int_mask;
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int cols;
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int rows;
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enum pl110_bppmode bpp;
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int invalidate;
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uint32_t mux_ctrl;
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uint32_t palette[256];
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uint32_t raw_palette[128];
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qemu_irq irq;
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} PL110State;
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static int vmstate_pl110_post_load(void *opaque, int version_id);
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static const VMStateDescription vmstate_pl110 = {
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.name = "pl110",
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.version_id = 2,
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.minimum_version_id = 1,
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.post_load = vmstate_pl110_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_INT32(version, PL110State),
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VMSTATE_UINT32_ARRAY(timing, PL110State, 4),
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VMSTATE_UINT32(cr, PL110State),
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VMSTATE_UINT32(upbase, PL110State),
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VMSTATE_UINT32(lpbase, PL110State),
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VMSTATE_UINT32(int_status, PL110State),
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VMSTATE_UINT32(int_mask, PL110State),
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VMSTATE_INT32(cols, PL110State),
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VMSTATE_INT32(rows, PL110State),
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VMSTATE_UINT32(bpp, PL110State),
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VMSTATE_INT32(invalidate, PL110State),
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VMSTATE_UINT32_ARRAY(palette, PL110State, 256),
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VMSTATE_UINT32_ARRAY(raw_palette, PL110State, 128),
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VMSTATE_UINT32_V(mux_ctrl, PL110State, 2),
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VMSTATE_END_OF_LIST()
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}
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};
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static const unsigned char pl110_id[] =
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{ 0x10, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
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static const unsigned char pl111_id[] = {
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0x11, 0x11, 0x24, 0x00, 0x0d, 0xf0, 0x05, 0xb1
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};
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/* Indexed by pl110_version */
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static const unsigned char *idregs[] = {
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pl110_id,
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/* The ARM documentation (DDI0224C) says the CLCDC on the Versatile board
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* has a different ID (0x93, 0x10, 0x04, 0x00, ...). However the hardware
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* itself has the same ID values as a stock PL110, and guests (in
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* particular Linux) rely on this. We emulate what the hardware does,
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* rather than what the docs claim it ought to do.
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*/
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pl110_id,
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pl111_id
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};
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#define BITS 8
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#include "pl110_template.h"
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#define BITS 15
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#include "pl110_template.h"
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#define BITS 16
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#include "pl110_template.h"
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#define BITS 24
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#include "pl110_template.h"
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#define BITS 32
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#include "pl110_template.h"
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static int pl110_enabled(PL110State *s)
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{
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return (s->cr & PL110_CR_EN) && (s->cr & PL110_CR_PWR);
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}
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static void pl110_update_display(void *opaque)
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{
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PL110State *s = (PL110State *)opaque;
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SysBusDevice *sbd;
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DisplaySurface *surface = qemu_console_surface(s->con);
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drawfn* fntable;
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drawfn fn;
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int dest_width;
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int src_width;
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int bpp_offset;
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int first;
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int last;
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if (!pl110_enabled(s)) {
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return;
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}
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sbd = SYS_BUS_DEVICE(s);
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switch (surface_bits_per_pixel(surface)) {
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case 0:
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return;
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case 8:
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fntable = pl110_draw_fn_8;
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dest_width = 1;
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break;
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case 15:
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fntable = pl110_draw_fn_15;
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dest_width = 2;
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break;
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case 16:
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fntable = pl110_draw_fn_16;
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dest_width = 2;
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break;
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case 24:
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fntable = pl110_draw_fn_24;
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dest_width = 3;
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break;
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case 32:
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fntable = pl110_draw_fn_32;
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dest_width = 4;
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break;
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default:
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fprintf(stderr, "pl110: Bad color depth\n");
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exit(1);
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}
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if (s->cr & PL110_CR_BGR)
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bpp_offset = 0;
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else
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bpp_offset = 24;
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if ((s->version != PL111) && (s->bpp == BPP_16)) {
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/* The PL110's native 16 bit mode is 5551; however
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* most boards with a PL110 implement an external
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* mux which allows bits to be reshuffled to give
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* 565 format. The mux is typically controlled by
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* an external system register.
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* This is controlled by a GPIO input pin
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* so boards can wire it up to their register.
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*
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* The PL111 straightforwardly implements both
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* 5551 and 565 under control of the bpp field
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* in the LCDControl register.
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*/
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switch (s->mux_ctrl) {
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case 3: /* 565 BGR */
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bpp_offset = (BPP_16_565 - BPP_16);
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break;
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case 1: /* 5551 */
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break;
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case 0: /* 888; also if we have loaded vmstate from an old version */
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case 2: /* 565 RGB */
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default:
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/* treat as 565 but honour BGR bit */
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bpp_offset += (BPP_16_565 - BPP_16);
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break;
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}
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}
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if (s->cr & PL110_CR_BEBO)
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fn = fntable[s->bpp + 8 + bpp_offset];
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else if (s->cr & PL110_CR_BEPO)
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fn = fntable[s->bpp + 16 + bpp_offset];
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else
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fn = fntable[s->bpp + bpp_offset];
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src_width = s->cols;
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switch (s->bpp) {
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case BPP_1:
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src_width >>= 3;
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break;
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case BPP_2:
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src_width >>= 2;
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break;
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case BPP_4:
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src_width >>= 1;
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break;
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case BPP_8:
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break;
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case BPP_16:
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case BPP_16_565:
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case BPP_12:
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src_width <<= 1;
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break;
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case BPP_32:
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src_width <<= 2;
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break;
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}
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dest_width *= s->cols;
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first = 0;
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if (s->invalidate) {
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framebuffer_update_memory_section(&s->fbsection,
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sysbus_address_space(sbd),
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s->upbase,
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s->rows, src_width);
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}
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framebuffer_update_display(surface, &s->fbsection,
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s->cols, s->rows,
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src_width, dest_width, 0,
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s->invalidate,
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fn, s->palette,
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&first, &last);
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if (first >= 0) {
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dpy_gfx_update(s->con, 0, first, s->cols, last - first + 1);
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}
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s->invalidate = 0;
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}
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static void pl110_invalidate_display(void * opaque)
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{
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PL110State *s = (PL110State *)opaque;
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s->invalidate = 1;
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if (pl110_enabled(s)) {
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qemu_console_resize(s->con, s->cols, s->rows);
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}
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}
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static void pl110_update_palette(PL110State *s, int n)
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{
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DisplaySurface *surface = qemu_console_surface(s->con);
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int i;
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uint32_t raw;
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unsigned int r, g, b;
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raw = s->raw_palette[n];
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n <<= 1;
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for (i = 0; i < 2; i++) {
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r = (raw & 0x1f) << 3;
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raw >>= 5;
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g = (raw & 0x1f) << 3;
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raw >>= 5;
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b = (raw & 0x1f) << 3;
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/* The I bit is ignored. */
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raw >>= 6;
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switch (surface_bits_per_pixel(surface)) {
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case 8:
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s->palette[n] = rgb_to_pixel8(r, g, b);
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break;
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case 15:
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s->palette[n] = rgb_to_pixel15(r, g, b);
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break;
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case 16:
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s->palette[n] = rgb_to_pixel16(r, g, b);
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break;
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case 24:
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case 32:
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s->palette[n] = rgb_to_pixel32(r, g, b);
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break;
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}
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n++;
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}
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}
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static void pl110_resize(PL110State *s, int width, int height)
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{
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if (width != s->cols || height != s->rows) {
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if (pl110_enabled(s)) {
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qemu_console_resize(s->con, width, height);
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}
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}
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s->cols = width;
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s->rows = height;
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}
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/* Update interrupts. */
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static void pl110_update(PL110State *s)
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{
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/* Raise IRQ if enabled and any status bit is 1 */
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if (s->int_status & s->int_mask) {
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qemu_irq_raise(s->irq);
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} else {
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qemu_irq_lower(s->irq);
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}
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}
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static void pl110_vblank_interrupt(void *opaque)
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{
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PL110State *s = opaque;
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/* Fire the vertical compare and next base IRQs and re-arm */
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s->int_status |= (PL110_IE_NB | PL110_IE_VC);
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timer_mod(s->vblank_timer,
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qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
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NANOSECONDS_PER_SECOND / 60);
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pl110_update(s);
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}
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static uint64_t pl110_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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PL110State *s = (PL110State *)opaque;
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if (offset >= 0xfe0 && offset < 0x1000) {
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return idregs[s->version][(offset - 0xfe0) >> 2];
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}
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if (offset >= 0x200 && offset < 0x400) {
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return s->raw_palette[(offset - 0x200) >> 2];
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}
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switch (offset >> 2) {
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case 0: /* LCDTiming0 */
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return s->timing[0];
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case 1: /* LCDTiming1 */
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return s->timing[1];
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case 2: /* LCDTiming2 */
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return s->timing[2];
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case 3: /* LCDTiming3 */
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return s->timing[3];
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case 4: /* LCDUPBASE */
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return s->upbase;
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case 5: /* LCDLPBASE */
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return s->lpbase;
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case 6: /* LCDIMSC */
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if (s->version != PL110) {
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return s->cr;
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}
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return s->int_mask;
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case 7: /* LCDControl */
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if (s->version != PL110) {
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return s->int_mask;
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}
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return s->cr;
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case 8: /* LCDRIS */
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return s->int_status;
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case 9: /* LCDMIS */
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return s->int_status & s->int_mask;
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case 11: /* LCDUPCURR */
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/* TODO: Implement vertical refresh. */
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return s->upbase;
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case 12: /* LCDLPCURR */
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return s->lpbase;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"pl110_read: Bad offset %x\n", (int)offset);
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return 0;
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}
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}
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static void pl110_write(void *opaque, hwaddr offset,
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uint64_t val, unsigned size)
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{
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PL110State *s = (PL110State *)opaque;
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int n;
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/* For simplicity invalidate the display whenever a control register
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is written to. */
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s->invalidate = 1;
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if (offset >= 0x200 && offset < 0x400) {
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/* Palette. */
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n = (offset - 0x200) >> 2;
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s->raw_palette[(offset - 0x200) >> 2] = val;
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pl110_update_palette(s, n);
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return;
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}
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switch (offset >> 2) {
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case 0: /* LCDTiming0 */
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s->timing[0] = val;
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n = ((val & 0xfc) + 4) * 4;
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pl110_resize(s, n, s->rows);
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break;
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case 1: /* LCDTiming1 */
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s->timing[1] = val;
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n = (val & 0x3ff) + 1;
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pl110_resize(s, s->cols, n);
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break;
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case 2: /* LCDTiming2 */
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s->timing[2] = val;
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break;
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case 3: /* LCDTiming3 */
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s->timing[3] = val;
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break;
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case 4: /* LCDUPBASE */
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s->upbase = val;
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break;
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case 5: /* LCDLPBASE */
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s->lpbase = val;
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break;
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case 6: /* LCDIMSC */
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if (s->version != PL110) {
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goto control;
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}
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imsc:
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s->int_mask = val;
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pl110_update(s);
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break;
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case 7: /* LCDControl */
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if (s->version != PL110) {
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goto imsc;
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}
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control:
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s->cr = val;
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s->bpp = (val >> 1) & 7;
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if (pl110_enabled(s)) {
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qemu_console_resize(s->con, s->cols, s->rows);
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timer_mod(s->vblank_timer,
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qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
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NANOSECONDS_PER_SECOND / 60);
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} else {
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timer_del(s->vblank_timer);
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}
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break;
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case 10: /* LCDICR */
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s->int_status &= ~val;
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pl110_update(s);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"pl110_write: Bad offset %x\n", (int)offset);
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}
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}
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static const MemoryRegionOps pl110_ops = {
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.read = pl110_read,
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.write = pl110_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void pl110_mux_ctrl_set(void *opaque, int line, int level)
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{
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PL110State *s = (PL110State *)opaque;
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s->mux_ctrl = level;
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}
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static int vmstate_pl110_post_load(void *opaque, int version_id)
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{
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PL110State *s = opaque;
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/* Make sure we redraw, and at the right size */
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pl110_invalidate_display(s);
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return 0;
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}
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|
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static const GraphicHwOps pl110_gfx_ops = {
|
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.invalidate = pl110_invalidate_display,
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.gfx_update = pl110_update_display,
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};
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static void pl110_realize(DeviceState *dev, Error **errp)
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{
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PL110State *s = PL110(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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memory_region_init_io(&s->iomem, OBJECT(s), &pl110_ops, s, "pl110", 0x1000);
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sysbus_init_mmio(sbd, &s->iomem);
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sysbus_init_irq(sbd, &s->irq);
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s->vblank_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
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pl110_vblank_interrupt, s);
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qdev_init_gpio_in(dev, pl110_mux_ctrl_set, 1);
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s->con = graphic_console_init(dev, 0, &pl110_gfx_ops, s);
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}
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|
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static void pl110_init(Object *obj)
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{
|
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PL110State *s = PL110(obj);
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|
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s->version = PL110;
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}
|
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|
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static void pl110_versatile_init(Object *obj)
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{
|
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PL110State *s = PL110(obj);
|
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|
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s->version = PL110_VERSATILE;
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}
|
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|
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static void pl111_init(Object *obj)
|
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{
|
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PL110State *s = PL110(obj);
|
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|
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s->version = PL111;
|
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}
|
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static void pl110_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
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dc->vmsd = &vmstate_pl110;
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dc->realize = pl110_realize;
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}
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static const TypeInfo pl110_info = {
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.name = TYPE_PL110,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(PL110State),
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.instance_init = pl110_init,
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.class_init = pl110_class_init,
|
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};
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static const TypeInfo pl110_versatile_info = {
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.name = "pl110_versatile",
|
|
.parent = TYPE_PL110,
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.instance_init = pl110_versatile_init,
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|
};
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|
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static const TypeInfo pl111_info = {
|
|
.name = "pl111",
|
|
.parent = TYPE_PL110,
|
|
.instance_init = pl111_init,
|
|
};
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|
|
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static void pl110_register_types(void)
|
|
{
|
|
type_register_static(&pl110_info);
|
|
type_register_static(&pl110_versatile_info);
|
|
type_register_static(&pl111_info);
|
|
}
|
|
|
|
type_init(pl110_register_types)
|