665 lines
18 KiB
C
665 lines
18 KiB
C
/*
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* QEMU model of Xilinx AXI-DMA block.
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*
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* Copyright (c) 2011 Edgar E. Iglesias.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#include "qapi/error.h"
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#include "qemu/timer.h"
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#include "hw/hw.h"
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#include "hw/irq.h"
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#include "hw/ptimer.h"
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#include "hw/qdev-properties.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "sysemu/dma.h"
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#include "hw/stream.h"
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#define D(x)
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#define TYPE_XILINX_AXI_DMA "xlnx.axi-dma"
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#define TYPE_XILINX_AXI_DMA_DATA_STREAM "xilinx-axi-dma-data-stream"
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#define TYPE_XILINX_AXI_DMA_CONTROL_STREAM "xilinx-axi-dma-control-stream"
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#define XILINX_AXI_DMA(obj) \
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OBJECT_CHECK(XilinxAXIDMA, (obj), TYPE_XILINX_AXI_DMA)
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#define XILINX_AXI_DMA_DATA_STREAM(obj) \
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OBJECT_CHECK(XilinxAXIDMAStreamSlave, (obj),\
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TYPE_XILINX_AXI_DMA_DATA_STREAM)
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#define XILINX_AXI_DMA_CONTROL_STREAM(obj) \
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OBJECT_CHECK(XilinxAXIDMAStreamSlave, (obj),\
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TYPE_XILINX_AXI_DMA_CONTROL_STREAM)
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#define R_DMACR (0x00 / 4)
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#define R_DMASR (0x04 / 4)
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#define R_CURDESC (0x08 / 4)
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#define R_TAILDESC (0x10 / 4)
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#define R_MAX (0x30 / 4)
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#define CONTROL_PAYLOAD_WORDS 5
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#define CONTROL_PAYLOAD_SIZE (CONTROL_PAYLOAD_WORDS * (sizeof(uint32_t)))
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typedef struct XilinxAXIDMA XilinxAXIDMA;
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typedef struct XilinxAXIDMAStreamSlave XilinxAXIDMAStreamSlave;
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enum {
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DMACR_RUNSTOP = 1,
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DMACR_TAILPTR_MODE = 2,
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DMACR_RESET = 4
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};
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enum {
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DMASR_HALTED = 1,
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DMASR_IDLE = 2,
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DMASR_IOC_IRQ = 1 << 12,
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DMASR_DLY_IRQ = 1 << 13,
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DMASR_IRQ_MASK = 7 << 12
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};
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struct SDesc {
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uint64_t nxtdesc;
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uint64_t buffer_address;
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uint64_t reserved;
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uint32_t control;
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uint32_t status;
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uint8_t app[CONTROL_PAYLOAD_SIZE];
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};
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enum {
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SDESC_CTRL_EOF = (1 << 26),
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SDESC_CTRL_SOF = (1 << 27),
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SDESC_CTRL_LEN_MASK = (1 << 23) - 1
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};
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enum {
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SDESC_STATUS_EOF = (1 << 26),
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SDESC_STATUS_SOF_BIT = 27,
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SDESC_STATUS_SOF = (1 << SDESC_STATUS_SOF_BIT),
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SDESC_STATUS_COMPLETE = (1 << 31)
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};
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struct Stream {
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struct XilinxAXIDMA *dma;
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ptimer_state *ptimer;
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qemu_irq irq;
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int nr;
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bool sof;
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struct SDesc desc;
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unsigned int complete_cnt;
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uint32_t regs[R_MAX];
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uint8_t app[20];
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unsigned char txbuf[16 * 1024];
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};
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struct XilinxAXIDMAStreamSlave {
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Object parent;
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struct XilinxAXIDMA *dma;
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};
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struct XilinxAXIDMA {
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SysBusDevice busdev;
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MemoryRegion iomem;
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MemoryRegion *dma_mr;
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AddressSpace as;
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uint32_t freqhz;
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StreamSlave *tx_data_dev;
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StreamSlave *tx_control_dev;
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XilinxAXIDMAStreamSlave rx_data_dev;
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XilinxAXIDMAStreamSlave rx_control_dev;
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struct Stream streams[2];
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StreamCanPushNotifyFn notify;
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void *notify_opaque;
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};
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/*
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* Helper calls to extract info from descriptors and other trivial
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* state from regs.
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*/
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static inline int stream_desc_sof(struct SDesc *d)
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{
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return d->control & SDESC_CTRL_SOF;
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}
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static inline int stream_desc_eof(struct SDesc *d)
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{
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return d->control & SDESC_CTRL_EOF;
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}
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static inline int stream_resetting(struct Stream *s)
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{
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return !!(s->regs[R_DMACR] & DMACR_RESET);
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}
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static inline int stream_running(struct Stream *s)
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{
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return s->regs[R_DMACR] & DMACR_RUNSTOP;
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}
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static inline int stream_idle(struct Stream *s)
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{
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return !!(s->regs[R_DMASR] & DMASR_IDLE);
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}
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static void stream_reset(struct Stream *s)
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{
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s->regs[R_DMASR] = DMASR_HALTED; /* starts up halted. */
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s->regs[R_DMACR] = 1 << 16; /* Starts with one in compl threshold. */
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s->sof = true;
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}
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/* Map an offset addr into a channel index. */
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static inline int streamid_from_addr(hwaddr addr)
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{
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int sid;
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sid = addr / (0x30);
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sid &= 1;
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return sid;
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}
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static void stream_desc_load(struct Stream *s, hwaddr addr)
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{
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struct SDesc *d = &s->desc;
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address_space_read(&s->dma->as, addr, MEMTXATTRS_UNSPECIFIED, d, sizeof *d);
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/* Convert from LE into host endianness. */
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d->buffer_address = le64_to_cpu(d->buffer_address);
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d->nxtdesc = le64_to_cpu(d->nxtdesc);
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d->control = le32_to_cpu(d->control);
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d->status = le32_to_cpu(d->status);
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}
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static void stream_desc_store(struct Stream *s, hwaddr addr)
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{
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struct SDesc *d = &s->desc;
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/* Convert from host endianness into LE. */
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d->buffer_address = cpu_to_le64(d->buffer_address);
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d->nxtdesc = cpu_to_le64(d->nxtdesc);
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d->control = cpu_to_le32(d->control);
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d->status = cpu_to_le32(d->status);
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address_space_write(&s->dma->as, addr, MEMTXATTRS_UNSPECIFIED,
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d, sizeof *d);
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}
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static void stream_update_irq(struct Stream *s)
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{
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unsigned int pending, mask, irq;
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pending = s->regs[R_DMASR] & DMASR_IRQ_MASK;
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mask = s->regs[R_DMACR] & DMASR_IRQ_MASK;
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irq = pending & mask;
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qemu_set_irq(s->irq, !!irq);
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}
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static void stream_reload_complete_cnt(struct Stream *s)
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{
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unsigned int comp_th;
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comp_th = (s->regs[R_DMACR] >> 16) & 0xff;
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s->complete_cnt = comp_th;
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}
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static void timer_hit(void *opaque)
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{
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struct Stream *s = opaque;
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stream_reload_complete_cnt(s);
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s->regs[R_DMASR] |= DMASR_DLY_IRQ;
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stream_update_irq(s);
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}
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static void stream_complete(struct Stream *s)
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{
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unsigned int comp_delay;
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/* Start the delayed timer. */
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ptimer_transaction_begin(s->ptimer);
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comp_delay = s->regs[R_DMACR] >> 24;
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if (comp_delay) {
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ptimer_stop(s->ptimer);
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ptimer_set_count(s->ptimer, comp_delay);
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ptimer_run(s->ptimer, 1);
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}
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s->complete_cnt--;
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if (s->complete_cnt == 0) {
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/* Raise the IOC irq. */
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s->regs[R_DMASR] |= DMASR_IOC_IRQ;
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stream_reload_complete_cnt(s);
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}
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ptimer_transaction_commit(s->ptimer);
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}
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static void stream_process_mem2s(struct Stream *s, StreamSlave *tx_data_dev,
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StreamSlave *tx_control_dev)
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{
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uint32_t prev_d;
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uint32_t txlen;
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uint64_t addr;
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bool eop;
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if (!stream_running(s) || stream_idle(s)) {
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return;
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}
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while (1) {
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stream_desc_load(s, s->regs[R_CURDESC]);
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if (s->desc.status & SDESC_STATUS_COMPLETE) {
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s->regs[R_DMASR] |= DMASR_HALTED;
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break;
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}
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if (stream_desc_sof(&s->desc)) {
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stream_push(tx_control_dev, s->desc.app, sizeof(s->desc.app), true);
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}
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txlen = s->desc.control & SDESC_CTRL_LEN_MASK;
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eop = stream_desc_eof(&s->desc);
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addr = s->desc.buffer_address;
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while (txlen) {
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unsigned int len;
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len = txlen > sizeof s->txbuf ? sizeof s->txbuf : txlen;
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address_space_read(&s->dma->as, addr,
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MEMTXATTRS_UNSPECIFIED,
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s->txbuf, len);
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stream_push(tx_data_dev, s->txbuf, len, eop && len == txlen);
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txlen -= len;
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addr += len;
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}
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if (eop) {
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stream_complete(s);
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}
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/* Update the descriptor. */
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s->desc.status = txlen | SDESC_STATUS_COMPLETE;
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stream_desc_store(s, s->regs[R_CURDESC]);
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/* Advance. */
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prev_d = s->regs[R_CURDESC];
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s->regs[R_CURDESC] = s->desc.nxtdesc;
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if (prev_d == s->regs[R_TAILDESC]) {
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s->regs[R_DMASR] |= DMASR_IDLE;
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break;
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}
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}
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}
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static size_t stream_process_s2mem(struct Stream *s, unsigned char *buf,
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size_t len, bool eop)
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{
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uint32_t prev_d;
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unsigned int rxlen;
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size_t pos = 0;
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if (!stream_running(s) || stream_idle(s)) {
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return 0;
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}
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while (len) {
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stream_desc_load(s, s->regs[R_CURDESC]);
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if (s->desc.status & SDESC_STATUS_COMPLETE) {
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s->regs[R_DMASR] |= DMASR_HALTED;
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break;
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}
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rxlen = s->desc.control & SDESC_CTRL_LEN_MASK;
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if (rxlen > len) {
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/* It fits. */
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rxlen = len;
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}
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address_space_write(&s->dma->as, s->desc.buffer_address,
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MEMTXATTRS_UNSPECIFIED, buf + pos, rxlen);
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len -= rxlen;
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pos += rxlen;
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/* Update the descriptor. */
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if (eop) {
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stream_complete(s);
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memcpy(s->desc.app, s->app, sizeof(s->desc.app));
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s->desc.status |= SDESC_STATUS_EOF;
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}
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s->desc.status |= s->sof << SDESC_STATUS_SOF_BIT;
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s->desc.status |= SDESC_STATUS_COMPLETE;
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stream_desc_store(s, s->regs[R_CURDESC]);
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s->sof = eop;
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/* Advance. */
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prev_d = s->regs[R_CURDESC];
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s->regs[R_CURDESC] = s->desc.nxtdesc;
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if (prev_d == s->regs[R_TAILDESC]) {
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s->regs[R_DMASR] |= DMASR_IDLE;
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break;
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}
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}
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return pos;
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}
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static void xilinx_axidma_reset(DeviceState *dev)
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{
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int i;
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XilinxAXIDMA *s = XILINX_AXI_DMA(dev);
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for (i = 0; i < 2; i++) {
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stream_reset(&s->streams[i]);
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}
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}
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static size_t
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xilinx_axidma_control_stream_push(StreamSlave *obj, unsigned char *buf,
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size_t len, bool eop)
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{
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XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM(obj);
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struct Stream *s = &cs->dma->streams[1];
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if (len != CONTROL_PAYLOAD_SIZE) {
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hw_error("AXI DMA requires %d byte control stream payload\n",
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(int)CONTROL_PAYLOAD_SIZE);
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}
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memcpy(s->app, buf, len);
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return len;
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}
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static bool
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xilinx_axidma_data_stream_can_push(StreamSlave *obj,
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StreamCanPushNotifyFn notify,
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void *notify_opaque)
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{
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XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
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struct Stream *s = &ds->dma->streams[1];
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if (!stream_running(s) || stream_idle(s)) {
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ds->dma->notify = notify;
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ds->dma->notify_opaque = notify_opaque;
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return false;
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}
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return true;
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}
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static size_t
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xilinx_axidma_data_stream_push(StreamSlave *obj, unsigned char *buf, size_t len,
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bool eop)
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{
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XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
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struct Stream *s = &ds->dma->streams[1];
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size_t ret;
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ret = stream_process_s2mem(s, buf, len, eop);
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stream_update_irq(s);
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return ret;
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}
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static uint64_t axidma_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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XilinxAXIDMA *d = opaque;
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struct Stream *s;
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uint32_t r = 0;
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int sid;
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sid = streamid_from_addr(addr);
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s = &d->streams[sid];
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addr = addr % 0x30;
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addr >>= 2;
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switch (addr) {
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case R_DMACR:
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/* Simulate one cycles reset delay. */
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s->regs[addr] &= ~DMACR_RESET;
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r = s->regs[addr];
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break;
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case R_DMASR:
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s->regs[addr] &= 0xffff;
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s->regs[addr] |= (s->complete_cnt & 0xff) << 16;
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s->regs[addr] |= (ptimer_get_count(s->ptimer) & 0xff) << 24;
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r = s->regs[addr];
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break;
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default:
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r = s->regs[addr];
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D(qemu_log("%s ch=%d addr=" TARGET_FMT_plx " v=%x\n",
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__func__, sid, addr * 4, r));
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break;
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}
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return r;
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}
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static void axidma_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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XilinxAXIDMA *d = opaque;
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struct Stream *s;
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int sid;
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sid = streamid_from_addr(addr);
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s = &d->streams[sid];
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addr = addr % 0x30;
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addr >>= 2;
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switch (addr) {
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case R_DMACR:
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/* Tailptr mode is always on. */
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value |= DMACR_TAILPTR_MODE;
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/* Remember our previous reset state. */
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value |= (s->regs[addr] & DMACR_RESET);
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s->regs[addr] = value;
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if (value & DMACR_RESET) {
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stream_reset(s);
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}
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if ((value & 1) && !stream_resetting(s)) {
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/* Start processing. */
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s->regs[R_DMASR] &= ~(DMASR_HALTED | DMASR_IDLE);
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}
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stream_reload_complete_cnt(s);
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break;
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case R_DMASR:
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/* Mask away write to clear irq lines. */
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value &= ~(value & DMASR_IRQ_MASK);
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s->regs[addr] = value;
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break;
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case R_TAILDESC:
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s->regs[addr] = value;
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s->regs[R_DMASR] &= ~DMASR_IDLE; /* Not idle. */
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if (!sid) {
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stream_process_mem2s(s, d->tx_data_dev, d->tx_control_dev);
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}
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break;
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default:
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D(qemu_log("%s: ch=%d addr=" TARGET_FMT_plx " v=%x\n",
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__func__, sid, addr * 4, (unsigned)value));
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s->regs[addr] = value;
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break;
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}
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if (sid == 1 && d->notify) {
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StreamCanPushNotifyFn notifytmp = d->notify;
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d->notify = NULL;
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notifytmp(d->notify_opaque);
|
|
}
|
|
stream_update_irq(s);
|
|
}
|
|
|
|
static const MemoryRegionOps axidma_ops = {
|
|
.read = axidma_read,
|
|
.write = axidma_write,
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
};
|
|
|
|
static void xilinx_axidma_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
XilinxAXIDMA *s = XILINX_AXI_DMA(dev);
|
|
XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(&s->rx_data_dev);
|
|
XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM(
|
|
&s->rx_control_dev);
|
|
int i;
|
|
|
|
object_property_add_link(OBJECT(ds), "dma", TYPE_XILINX_AXI_DMA,
|
|
(Object **)&ds->dma,
|
|
object_property_allow_set_link,
|
|
OBJ_PROP_LINK_STRONG);
|
|
object_property_add_link(OBJECT(cs), "dma", TYPE_XILINX_AXI_DMA,
|
|
(Object **)&cs->dma,
|
|
object_property_allow_set_link,
|
|
OBJ_PROP_LINK_STRONG);
|
|
object_property_set_link(OBJECT(ds), "dma", OBJECT(s), &error_abort);
|
|
object_property_set_link(OBJECT(cs), "dma", OBJECT(s), &error_abort);
|
|
|
|
for (i = 0; i < 2; i++) {
|
|
struct Stream *st = &s->streams[i];
|
|
|
|
st->dma = s;
|
|
st->nr = i;
|
|
st->ptimer = ptimer_init(timer_hit, st, PTIMER_POLICY_DEFAULT);
|
|
ptimer_transaction_begin(st->ptimer);
|
|
ptimer_set_freq(st->ptimer, s->freqhz);
|
|
ptimer_transaction_commit(st->ptimer);
|
|
}
|
|
|
|
address_space_init(&s->as,
|
|
s->dma_mr ? s->dma_mr : get_system_memory(), "dma");
|
|
}
|
|
|
|
static void xilinx_axidma_init(Object *obj)
|
|
{
|
|
XilinxAXIDMA *s = XILINX_AXI_DMA(obj);
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
|
|
|
|
object_initialize_child(OBJECT(s), "axistream-connected-target",
|
|
&s->rx_data_dev, TYPE_XILINX_AXI_DMA_DATA_STREAM);
|
|
object_initialize_child(OBJECT(s), "axistream-control-connected-target",
|
|
&s->rx_control_dev,
|
|
TYPE_XILINX_AXI_DMA_CONTROL_STREAM);
|
|
object_property_add_link(obj, "dma", TYPE_MEMORY_REGION,
|
|
(Object **)&s->dma_mr,
|
|
qdev_prop_allow_set_link_before_realize,
|
|
OBJ_PROP_LINK_STRONG);
|
|
|
|
sysbus_init_irq(sbd, &s->streams[0].irq);
|
|
sysbus_init_irq(sbd, &s->streams[1].irq);
|
|
|
|
memory_region_init_io(&s->iomem, obj, &axidma_ops, s,
|
|
"xlnx.axi-dma", R_MAX * 4 * 2);
|
|
sysbus_init_mmio(sbd, &s->iomem);
|
|
}
|
|
|
|
static Property axidma_properties[] = {
|
|
DEFINE_PROP_UINT32("freqhz", XilinxAXIDMA, freqhz, 50000000),
|
|
DEFINE_PROP_LINK("axistream-connected", XilinxAXIDMA,
|
|
tx_data_dev, TYPE_STREAM_SLAVE, StreamSlave *),
|
|
DEFINE_PROP_LINK("axistream-control-connected", XilinxAXIDMA,
|
|
tx_control_dev, TYPE_STREAM_SLAVE, StreamSlave *),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void axidma_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
dc->realize = xilinx_axidma_realize,
|
|
dc->reset = xilinx_axidma_reset;
|
|
device_class_set_props(dc, axidma_properties);
|
|
}
|
|
|
|
static StreamSlaveClass xilinx_axidma_data_stream_class = {
|
|
.push = xilinx_axidma_data_stream_push,
|
|
.can_push = xilinx_axidma_data_stream_can_push,
|
|
};
|
|
|
|
static StreamSlaveClass xilinx_axidma_control_stream_class = {
|
|
.push = xilinx_axidma_control_stream_push,
|
|
};
|
|
|
|
static void xilinx_axidma_stream_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass);
|
|
|
|
ssc->push = ((StreamSlaveClass *)data)->push;
|
|
ssc->can_push = ((StreamSlaveClass *)data)->can_push;
|
|
}
|
|
|
|
static const TypeInfo axidma_info = {
|
|
.name = TYPE_XILINX_AXI_DMA,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(XilinxAXIDMA),
|
|
.class_init = axidma_class_init,
|
|
.instance_init = xilinx_axidma_init,
|
|
};
|
|
|
|
static const TypeInfo xilinx_axidma_data_stream_info = {
|
|
.name = TYPE_XILINX_AXI_DMA_DATA_STREAM,
|
|
.parent = TYPE_OBJECT,
|
|
.instance_size = sizeof(struct XilinxAXIDMAStreamSlave),
|
|
.class_init = xilinx_axidma_stream_class_init,
|
|
.class_data = &xilinx_axidma_data_stream_class,
|
|
.interfaces = (InterfaceInfo[]) {
|
|
{ TYPE_STREAM_SLAVE },
|
|
{ }
|
|
}
|
|
};
|
|
|
|
static const TypeInfo xilinx_axidma_control_stream_info = {
|
|
.name = TYPE_XILINX_AXI_DMA_CONTROL_STREAM,
|
|
.parent = TYPE_OBJECT,
|
|
.instance_size = sizeof(struct XilinxAXIDMAStreamSlave),
|
|
.class_init = xilinx_axidma_stream_class_init,
|
|
.class_data = &xilinx_axidma_control_stream_class,
|
|
.interfaces = (InterfaceInfo[]) {
|
|
{ TYPE_STREAM_SLAVE },
|
|
{ }
|
|
}
|
|
};
|
|
|
|
static void xilinx_axidma_register_types(void)
|
|
{
|
|
type_register_static(&axidma_info);
|
|
type_register_static(&xilinx_axidma_data_stream_info);
|
|
type_register_static(&xilinx_axidma_control_stream_info);
|
|
}
|
|
|
|
type_init(xilinx_axidma_register_types)
|