462 lines
15 KiB
C
462 lines
15 KiB
C
/*
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* Samsung exynos4210 Interrupt Combiner
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*
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* Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
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* All rights reserved.
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*
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* Evgeny Voevodin <e.voevodin@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* Exynos4210 Combiner represents an OR gate for SOC's IRQ lines. It combines
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* IRQ sources into groups and provides signal output to GIC from each group. It
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* is driven by common mask and enable/disable logic. Take a note that not all
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* IRQs are passed to GIC through Combiner.
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*/
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "qemu/module.h"
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#include "hw/arm/exynos4210.h"
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#include "hw/hw.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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//#define DEBUG_COMBINER
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#ifdef DEBUG_COMBINER
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#define DPRINTF(fmt, ...) \
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do { fprintf(stdout, "COMBINER: [%s:%d] " fmt, __func__ , __LINE__, \
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## __VA_ARGS__); } while (0)
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#else
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#define DPRINTF(fmt, ...) do {} while (0)
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#endif
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#define IIC_NGRP 64 /* Internal Interrupt Combiner
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Groups number */
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#define IIC_NIRQ (IIC_NGRP * 8)/* Internal Interrupt Combiner
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Interrupts number */
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#define IIC_REGION_SIZE 0x108 /* Size of memory mapped region */
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#define IIC_REGSET_SIZE 0x41
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/*
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* State for each output signal of internal combiner
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*/
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typedef struct CombinerGroupState {
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uint8_t src_mask; /* 1 - source enabled, 0 - disabled */
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uint8_t src_pending; /* Pending source interrupts before masking */
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} CombinerGroupState;
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#define TYPE_EXYNOS4210_COMBINER "exynos4210.combiner"
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#define EXYNOS4210_COMBINER(obj) \
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OBJECT_CHECK(Exynos4210CombinerState, (obj), TYPE_EXYNOS4210_COMBINER)
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typedef struct Exynos4210CombinerState {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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struct CombinerGroupState group[IIC_NGRP];
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uint32_t reg_set[IIC_REGSET_SIZE];
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uint32_t icipsr[2];
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uint32_t external; /* 1 means that this combiner is external */
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qemu_irq output_irq[IIC_NGRP];
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} Exynos4210CombinerState;
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static const VMStateDescription vmstate_exynos4210_combiner_group_state = {
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.name = "exynos4210.combiner.groupstate",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT8(src_mask, CombinerGroupState),
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VMSTATE_UINT8(src_pending, CombinerGroupState),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_exynos4210_combiner = {
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.name = "exynos4210.combiner",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_STRUCT_ARRAY(group, Exynos4210CombinerState, IIC_NGRP, 0,
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vmstate_exynos4210_combiner_group_state, CombinerGroupState),
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VMSTATE_UINT32_ARRAY(reg_set, Exynos4210CombinerState,
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IIC_REGSET_SIZE),
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VMSTATE_UINT32_ARRAY(icipsr, Exynos4210CombinerState, 2),
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VMSTATE_UINT32(external, Exynos4210CombinerState),
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VMSTATE_END_OF_LIST()
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}
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};
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/*
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* Get Combiner input GPIO into irqs structure
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*/
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void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, DeviceState *dev,
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int ext)
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{
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int n;
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int bit;
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int max;
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qemu_irq *irq;
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max = ext ? EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ :
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EXYNOS4210_MAX_INT_COMBINER_IN_IRQ;
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irq = ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq;
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/*
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* Some IRQs of Int/External Combiner are going to two Combiners groups,
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* so let split them.
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*/
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for (n = 0; n < max; n++) {
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bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n);
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switch (n) {
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/* MDNIE_LCD1 INTG1 */
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case EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 0) ...
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EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 3):
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irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
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irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(0, bit + 4)]);
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continue;
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/* TMU INTG3 */
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case EXYNOS4210_COMBINER_GET_IRQ_NUM(3, 4):
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irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
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irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(2, bit)]);
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continue;
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/* LCD1 INTG12 */
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case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 0) ...
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EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 3):
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irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
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irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(11, bit + 4)]);
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continue;
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/* Multi-Core Timer INTG12 */
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case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4) ...
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EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 8):
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irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
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irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
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continue;
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/* Multi-Core Timer INTG35 */
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case EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 4) ...
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EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 8):
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irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
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irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
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continue;
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/* Multi-Core Timer INTG51 */
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case EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 4) ...
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EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 8):
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irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
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irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
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continue;
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/* Multi-Core Timer INTG53 */
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case EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 4) ...
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EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 8):
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irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
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irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
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continue;
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}
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irq[n] = qdev_get_gpio_in(dev, n);
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}
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}
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static uint64_t
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exynos4210_combiner_read(void *opaque, hwaddr offset, unsigned size)
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{
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struct Exynos4210CombinerState *s =
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(struct Exynos4210CombinerState *)opaque;
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uint32_t req_quad_base_n; /* Base of registers quad. Multiply it by 4 and
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get a start of corresponding group quad */
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uint32_t grp_quad_base_n; /* Base of group quad */
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uint32_t reg_n; /* Register number inside the quad */
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uint32_t val;
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req_quad_base_n = offset >> 4;
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grp_quad_base_n = req_quad_base_n << 2;
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reg_n = (offset - (req_quad_base_n << 4)) >> 2;
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if (req_quad_base_n >= IIC_NGRP) {
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/* Read of ICIPSR register */
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return s->icipsr[reg_n];
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}
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val = 0;
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switch (reg_n) {
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/* IISTR */
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case 2:
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val |= s->group[grp_quad_base_n].src_pending;
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val |= s->group[grp_quad_base_n + 1].src_pending << 8;
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val |= s->group[grp_quad_base_n + 2].src_pending << 16;
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val |= s->group[grp_quad_base_n + 3].src_pending << 24;
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break;
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/* IIMSR */
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case 3:
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val |= s->group[grp_quad_base_n].src_mask &
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s->group[grp_quad_base_n].src_pending;
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val |= (s->group[grp_quad_base_n + 1].src_mask &
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s->group[grp_quad_base_n + 1].src_pending) << 8;
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val |= (s->group[grp_quad_base_n + 2].src_mask &
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s->group[grp_quad_base_n + 2].src_pending) << 16;
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val |= (s->group[grp_quad_base_n + 3].src_mask &
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s->group[grp_quad_base_n + 3].src_pending) << 24;
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break;
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default:
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if (offset >> 2 >= IIC_REGSET_SIZE) {
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hw_error("exynos4210.combiner: overflow of reg_set by 0x"
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TARGET_FMT_plx "offset\n", offset);
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}
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val = s->reg_set[offset >> 2];
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return 0;
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}
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return val;
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}
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static void exynos4210_combiner_update(void *opaque, uint8_t group_n)
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{
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struct Exynos4210CombinerState *s =
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(struct Exynos4210CombinerState *)opaque;
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/* Send interrupt if needed */
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if (s->group[group_n].src_mask & s->group[group_n].src_pending) {
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#ifdef DEBUG_COMBINER
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if (group_n != 26) {
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/* skip uart */
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DPRINTF("%s raise IRQ[%d]\n", s->external ? "EXT" : "INT", group_n);
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}
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#endif
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/* Set Combiner interrupt pending status after masking */
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if (group_n >= 32) {
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s->icipsr[1] |= 1 << (group_n - 32);
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} else {
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s->icipsr[0] |= 1 << group_n;
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}
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qemu_irq_raise(s->output_irq[group_n]);
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} else {
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#ifdef DEBUG_COMBINER
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if (group_n != 26) {
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/* skip uart */
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DPRINTF("%s lower IRQ[%d]\n", s->external ? "EXT" : "INT", group_n);
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}
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#endif
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/* Set Combiner interrupt pending status after masking */
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if (group_n >= 32) {
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s->icipsr[1] &= ~(1 << (group_n - 32));
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} else {
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s->icipsr[0] &= ~(1 << group_n);
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}
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qemu_irq_lower(s->output_irq[group_n]);
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}
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}
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static void exynos4210_combiner_write(void *opaque, hwaddr offset,
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uint64_t val, unsigned size)
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{
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struct Exynos4210CombinerState *s =
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(struct Exynos4210CombinerState *)opaque;
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uint32_t req_quad_base_n; /* Base of registers quad. Multiply it by 4 and
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get a start of corresponding group quad */
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uint32_t grp_quad_base_n; /* Base of group quad */
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uint32_t reg_n; /* Register number inside the quad */
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req_quad_base_n = offset >> 4;
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grp_quad_base_n = req_quad_base_n << 2;
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reg_n = (offset - (req_quad_base_n << 4)) >> 2;
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if (req_quad_base_n >= IIC_NGRP) {
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hw_error("exynos4210.combiner: unallowed write access at offset 0x"
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TARGET_FMT_plx "\n", offset);
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return;
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}
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if (reg_n > 1) {
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hw_error("exynos4210.combiner: unallowed write access at offset 0x"
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TARGET_FMT_plx "\n", offset);
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return;
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}
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if (offset >> 2 >= IIC_REGSET_SIZE) {
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hw_error("exynos4210.combiner: overflow of reg_set by 0x"
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TARGET_FMT_plx "offset\n", offset);
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}
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s->reg_set[offset >> 2] = val;
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switch (reg_n) {
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/* IIESR */
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case 0:
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/* FIXME: what if irq is pending, allowed by mask, and we allow it
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* again. Interrupt will rise again! */
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DPRINTF("%s enable IRQ for groups %d, %d, %d, %d\n",
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s->external ? "EXT" : "INT",
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grp_quad_base_n,
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grp_quad_base_n + 1,
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grp_quad_base_n + 2,
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grp_quad_base_n + 3);
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/* Enable interrupt sources */
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s->group[grp_quad_base_n].src_mask |= val & 0xFF;
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s->group[grp_quad_base_n + 1].src_mask |= (val & 0xFF00) >> 8;
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s->group[grp_quad_base_n + 2].src_mask |= (val & 0xFF0000) >> 16;
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s->group[grp_quad_base_n + 3].src_mask |= (val & 0xFF000000) >> 24;
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exynos4210_combiner_update(s, grp_quad_base_n);
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exynos4210_combiner_update(s, grp_quad_base_n + 1);
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exynos4210_combiner_update(s, grp_quad_base_n + 2);
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exynos4210_combiner_update(s, grp_quad_base_n + 3);
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break;
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/* IIECR */
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case 1:
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DPRINTF("%s disable IRQ for groups %d, %d, %d, %d\n",
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s->external ? "EXT" : "INT",
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grp_quad_base_n,
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grp_quad_base_n + 1,
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grp_quad_base_n + 2,
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grp_quad_base_n + 3);
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/* Disable interrupt sources */
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s->group[grp_quad_base_n].src_mask &= ~(val & 0xFF);
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s->group[grp_quad_base_n + 1].src_mask &= ~((val & 0xFF00) >> 8);
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s->group[grp_quad_base_n + 2].src_mask &= ~((val & 0xFF0000) >> 16);
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s->group[grp_quad_base_n + 3].src_mask &= ~((val & 0xFF000000) >> 24);
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exynos4210_combiner_update(s, grp_quad_base_n);
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exynos4210_combiner_update(s, grp_quad_base_n + 1);
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exynos4210_combiner_update(s, grp_quad_base_n + 2);
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exynos4210_combiner_update(s, grp_quad_base_n + 3);
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break;
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default:
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hw_error("exynos4210.combiner: unallowed write access at offset 0x"
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TARGET_FMT_plx "\n", offset);
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break;
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}
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}
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/* Get combiner group and bit from irq number */
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static uint8_t get_combiner_group_and_bit(int irq, uint8_t *bit)
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{
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*bit = irq - ((irq >> 3) << 3);
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return irq >> 3;
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}
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/* Process a change in an external IRQ input. */
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static void exynos4210_combiner_handler(void *opaque, int irq, int level)
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{
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struct Exynos4210CombinerState *s =
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(struct Exynos4210CombinerState *)opaque;
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uint8_t bit_n, group_n;
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group_n = get_combiner_group_and_bit(irq, &bit_n);
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if (s->external && group_n >= EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ) {
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DPRINTF("%s unallowed IRQ group 0x%x\n", s->external ? "EXT" : "INT"
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, group_n);
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return;
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}
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if (level) {
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s->group[group_n].src_pending |= 1 << bit_n;
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} else {
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s->group[group_n].src_pending &= ~(1 << bit_n);
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}
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exynos4210_combiner_update(s, group_n);
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}
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static void exynos4210_combiner_reset(DeviceState *d)
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{
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struct Exynos4210CombinerState *s = (struct Exynos4210CombinerState *)d;
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memset(&s->group, 0, sizeof(s->group));
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memset(&s->reg_set, 0, sizeof(s->reg_set));
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s->reg_set[0xC0 >> 2] = 0x01010101;
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s->reg_set[0xC4 >> 2] = 0x01010101;
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s->reg_set[0xD0 >> 2] = 0x01010101;
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s->reg_set[0xD4 >> 2] = 0x01010101;
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}
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static const MemoryRegionOps exynos4210_combiner_ops = {
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.read = exynos4210_combiner_read,
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.write = exynos4210_combiner_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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/*
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* Internal Combiner initialization.
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*/
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static void exynos4210_combiner_init(Object *obj)
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{
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DeviceState *dev = DEVICE(obj);
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Exynos4210CombinerState *s = EXYNOS4210_COMBINER(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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unsigned int i;
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/* Allocate general purpose input signals and connect a handler to each of
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* them */
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qdev_init_gpio_in(dev, exynos4210_combiner_handler, IIC_NIRQ);
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/* Connect SysBusDev irqs to device specific irqs */
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for (i = 0; i < IIC_NGRP; i++) {
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sysbus_init_irq(sbd, &s->output_irq[i]);
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}
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memory_region_init_io(&s->iomem, obj, &exynos4210_combiner_ops, s,
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"exynos4210-combiner", IIC_REGION_SIZE);
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sysbus_init_mmio(sbd, &s->iomem);
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}
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static Property exynos4210_combiner_properties[] = {
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DEFINE_PROP_UINT32("external", Exynos4210CombinerState, external, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void exynos4210_combiner_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = exynos4210_combiner_reset;
|
|
device_class_set_props(dc, exynos4210_combiner_properties);
|
|
dc->vmsd = &vmstate_exynos4210_combiner;
|
|
}
|
|
|
|
static const TypeInfo exynos4210_combiner_info = {
|
|
.name = TYPE_EXYNOS4210_COMBINER,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(Exynos4210CombinerState),
|
|
.instance_init = exynos4210_combiner_init,
|
|
.class_init = exynos4210_combiner_class_init,
|
|
};
|
|
|
|
static void exynos4210_combiner_register_types(void)
|
|
{
|
|
type_register_static(&exynos4210_combiner_info);
|
|
}
|
|
|
|
type_init(exynos4210_combiner_register_types)
|