397 lines
10 KiB
C
397 lines
10 KiB
C
/*
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* RX Interrupt Control Unit
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*
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* Warning: Only ICUa is supported.
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*
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* Datasheet: RX62N Group, RX621 Group User's Manual: Hardware
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* (Rev.1.40 R01UH0033EJ0140)
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*
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* Copyright (c) 2019 Yoshinori Sato
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/error-report.h"
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#include "hw/irq.h"
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#include "hw/registerfields.h"
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#include "hw/qdev-properties.h"
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#include "hw/intc/rx_icu.h"
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#include "migration/vmstate.h"
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REG8(IR, 0)
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FIELD(IR, IR, 0, 1)
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REG8(DTCER, 0x100)
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FIELD(DTCER, DTCE, 0, 1)
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REG8(IER, 0x200)
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REG8(SWINTR, 0x2e0)
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FIELD(SWINTR, SWINT, 0, 1)
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REG16(FIR, 0x2f0)
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FIELD(FIR, FVCT, 0, 8)
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FIELD(FIR, FIEN, 15, 1)
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REG8(IPR, 0x300)
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FIELD(IPR, IPR, 0, 4)
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REG8(DMRSR, 0x400)
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REG8(IRQCR, 0x500)
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FIELD(IRQCR, IRQMD, 2, 2)
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REG8(NMISR, 0x580)
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FIELD(NMISR, NMIST, 0, 1)
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FIELD(NMISR, LVDST, 1, 1)
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FIELD(NMISR, OSTST, 2, 1)
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REG8(NMIER, 0x581)
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FIELD(NMIER, NMIEN, 0, 1)
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FIELD(NMIER, LVDEN, 1, 1)
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FIELD(NMIER, OSTEN, 2, 1)
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REG8(NMICLR, 0x582)
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FIELD(NMICLR, NMICLR, 0, 1)
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FIELD(NMICLR, OSTCLR, 2, 1)
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REG8(NMICR, 0x583)
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FIELD(NMICR, NMIMD, 3, 1)
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static void set_irq(RXICUState *icu, int n_IRQ, int req)
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{
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if ((icu->fir & R_FIR_FIEN_MASK) &&
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(icu->fir & R_FIR_FVCT_MASK) == n_IRQ) {
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qemu_set_irq(icu->_fir, req);
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} else {
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qemu_set_irq(icu->_irq, req);
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}
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}
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static uint16_t rxicu_level(RXICUState *icu, unsigned n)
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{
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return (icu->ipr[icu->map[n]] << 8) | n;
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}
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static void rxicu_request(RXICUState *icu, int n_IRQ)
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{
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int enable;
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enable = icu->ier[n_IRQ / 8] & (1 << (n_IRQ & 7));
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if (n_IRQ > 0 && enable != 0 && atomic_read(&icu->req_irq) < 0) {
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atomic_set(&icu->req_irq, n_IRQ);
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set_irq(icu, n_IRQ, rxicu_level(icu, n_IRQ));
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}
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}
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static void rxicu_set_irq(void *opaque, int n_IRQ, int level)
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{
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RXICUState *icu = opaque;
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struct IRQSource *src;
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int issue;
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if (n_IRQ >= NR_IRQS) {
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error_report("%s: IRQ %d out of range", __func__, n_IRQ);
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return;
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}
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src = &icu->src[n_IRQ];
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level = (level != 0);
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switch (src->sense) {
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case TRG_LEVEL:
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/* level-sensitive irq */
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issue = level;
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src->level = level;
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break;
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case TRG_NEDGE:
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issue = (level == 0 && src->level == 1);
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src->level = level;
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break;
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case TRG_PEDGE:
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issue = (level == 1 && src->level == 0);
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src->level = level;
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break;
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case TRG_BEDGE:
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issue = ((level ^ src->level) & 1);
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src->level = level;
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break;
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default:
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g_assert_not_reached();
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}
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if (issue == 0 && src->sense == TRG_LEVEL) {
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icu->ir[n_IRQ] = 0;
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if (atomic_read(&icu->req_irq) == n_IRQ) {
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/* clear request */
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set_irq(icu, n_IRQ, 0);
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atomic_set(&icu->req_irq, -1);
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}
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return;
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}
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if (issue) {
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icu->ir[n_IRQ] = 1;
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rxicu_request(icu, n_IRQ);
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}
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}
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static void rxicu_ack_irq(void *opaque, int no, int level)
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{
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RXICUState *icu = opaque;
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int i;
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int n_IRQ;
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int max_pri;
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n_IRQ = atomic_read(&icu->req_irq);
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if (n_IRQ < 0) {
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return;
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}
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atomic_set(&icu->req_irq, -1);
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if (icu->src[n_IRQ].sense != TRG_LEVEL) {
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icu->ir[n_IRQ] = 0;
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}
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max_pri = 0;
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n_IRQ = -1;
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for (i = 0; i < NR_IRQS; i++) {
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if (icu->ir[i]) {
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if (max_pri < icu->ipr[icu->map[i]]) {
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n_IRQ = i;
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max_pri = icu->ipr[icu->map[i]];
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}
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}
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}
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if (n_IRQ >= 0) {
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rxicu_request(icu, n_IRQ);
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}
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}
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static uint64_t icu_read(void *opaque, hwaddr addr, unsigned size)
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{
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RXICUState *icu = opaque;
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int reg = addr & 0xff;
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if ((addr != A_FIR && size != 1) ||
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(addr == A_FIR && size != 2)) {
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qemu_log_mask(LOG_GUEST_ERROR, "rx_icu: Invalid read size 0x%"
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HWADDR_PRIX "\n",
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addr);
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return UINT64_MAX;
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}
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switch (addr) {
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case A_IR ... A_IR + 0xff:
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return icu->ir[reg] & R_IR_IR_MASK;
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case A_DTCER ... A_DTCER + 0xff:
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return icu->dtcer[reg] & R_DTCER_DTCE_MASK;
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case A_IER ... A_IER + 0x1f:
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return icu->ier[reg];
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case A_SWINTR:
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return 0;
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case A_FIR:
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return icu->fir & (R_FIR_FIEN_MASK | R_FIR_FVCT_MASK);
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case A_IPR ... A_IPR + 0x8f:
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return icu->ipr[reg] & R_IPR_IPR_MASK;
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case A_DMRSR:
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case A_DMRSR + 4:
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case A_DMRSR + 8:
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case A_DMRSR + 12:
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return icu->dmasr[reg >> 2];
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case A_IRQCR ... A_IRQCR + 0x1f:
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return icu->src[64 + reg].sense << R_IRQCR_IRQMD_SHIFT;
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case A_NMISR:
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case A_NMICLR:
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return 0;
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case A_NMIER:
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return icu->nmier;
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case A_NMICR:
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return icu->nmicr;
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default:
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qemu_log_mask(LOG_UNIMP, "rx_icu: Register 0x%" HWADDR_PRIX " "
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"not implemented.\n",
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addr);
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break;
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}
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return UINT64_MAX;
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}
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static void icu_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
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{
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RXICUState *icu = opaque;
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int reg = addr & 0xff;
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if ((addr != A_FIR && size != 1) ||
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(addr == A_FIR && size != 2)) {
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qemu_log_mask(LOG_GUEST_ERROR, "rx_icu: Invalid write size at "
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"0x%" HWADDR_PRIX "\n",
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addr);
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return;
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}
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switch (addr) {
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case A_IR ... A_IR + 0xff:
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if (icu->src[reg].sense != TRG_LEVEL && val == 0) {
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icu->ir[reg] = 0;
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}
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break;
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case A_DTCER ... A_DTCER + 0xff:
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icu->dtcer[reg] = val & R_DTCER_DTCE_MASK;
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qemu_log_mask(LOG_UNIMP, "rx_icu: DTC not implemented\n");
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break;
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case A_IER ... A_IER + 0x1f:
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icu->ier[reg] = val;
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break;
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case A_SWINTR:
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if (val & R_SWINTR_SWINT_MASK) {
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qemu_irq_pulse(icu->_swi);
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}
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break;
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case A_FIR:
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icu->fir = val & (R_FIR_FIEN_MASK | R_FIR_FVCT_MASK);
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break;
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case A_IPR ... A_IPR + 0x8f:
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icu->ipr[reg] = val & R_IPR_IPR_MASK;
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break;
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case A_DMRSR:
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case A_DMRSR + 4:
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case A_DMRSR + 8:
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case A_DMRSR + 12:
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icu->dmasr[reg >> 2] = val;
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qemu_log_mask(LOG_UNIMP, "rx_icu: DMAC not implemented\n");
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break;
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case A_IRQCR ... A_IRQCR + 0x1f:
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icu->src[64 + reg].sense = val >> R_IRQCR_IRQMD_SHIFT;
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break;
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case A_NMICLR:
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break;
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case A_NMIER:
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icu->nmier |= val & (R_NMIER_NMIEN_MASK |
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R_NMIER_LVDEN_MASK |
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R_NMIER_OSTEN_MASK);
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break;
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case A_NMICR:
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if ((icu->nmier & R_NMIER_NMIEN_MASK) == 0) {
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icu->nmicr = val & R_NMICR_NMIMD_MASK;
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}
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "rx_icu: Register 0x%" HWADDR_PRIX " "
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"not implemented\n",
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addr);
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break;
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}
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}
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static const MemoryRegionOps icu_ops = {
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.write = icu_write,
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.read = icu_read,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl = {
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.min_access_size = 1,
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.max_access_size = 2,
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},
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.valid = {
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.min_access_size = 1,
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.max_access_size = 2,
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},
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};
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static void rxicu_realize(DeviceState *dev, Error **errp)
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{
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RXICUState *icu = RX_ICU(dev);
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int i, j;
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if (icu->init_sense == NULL) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"rx_icu: trigger-level property must be set.");
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return;
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}
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for (i = j = 0; i < NR_IRQS; i++) {
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if (icu->init_sense[j] == i) {
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icu->src[i].sense = TRG_LEVEL;
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if (j < icu->nr_sense) {
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j++;
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}
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} else {
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icu->src[i].sense = TRG_PEDGE;
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}
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}
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icu->req_irq = -1;
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}
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static void rxicu_init(Object *obj)
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{
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SysBusDevice *d = SYS_BUS_DEVICE(obj);
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RXICUState *icu = RX_ICU(obj);
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memory_region_init_io(&icu->memory, OBJECT(icu), &icu_ops,
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icu, "rx-icu", 0x600);
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sysbus_init_mmio(d, &icu->memory);
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qdev_init_gpio_in(DEVICE(d), rxicu_set_irq, NR_IRQS);
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qdev_init_gpio_in_named(DEVICE(d), rxicu_ack_irq, "ack", 1);
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sysbus_init_irq(d, &icu->_irq);
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sysbus_init_irq(d, &icu->_fir);
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sysbus_init_irq(d, &icu->_swi);
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}
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static void rxicu_fini(Object *obj)
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{
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RXICUState *icu = RX_ICU(obj);
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g_free(icu->map);
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g_free(icu->init_sense);
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}
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static const VMStateDescription vmstate_rxicu = {
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.name = "rx-icu",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT8_ARRAY(ir, RXICUState, NR_IRQS),
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VMSTATE_UINT8_ARRAY(dtcer, RXICUState, NR_IRQS),
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VMSTATE_UINT8_ARRAY(ier, RXICUState, NR_IRQS / 8),
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VMSTATE_UINT8_ARRAY(ipr, RXICUState, 142),
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VMSTATE_UINT8_ARRAY(dmasr, RXICUState, 4),
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VMSTATE_UINT16(fir, RXICUState),
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VMSTATE_UINT8(nmisr, RXICUState),
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VMSTATE_UINT8(nmier, RXICUState),
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VMSTATE_UINT8(nmiclr, RXICUState),
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VMSTATE_UINT8(nmicr, RXICUState),
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VMSTATE_INT16(req_irq, RXICUState),
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VMSTATE_END_OF_LIST()
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}
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};
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static Property rxicu_properties[] = {
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DEFINE_PROP_ARRAY("ipr-map", RXICUState, nr_irqs, map,
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qdev_prop_uint8, uint8_t),
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DEFINE_PROP_ARRAY("trigger-level", RXICUState, nr_sense, init_sense,
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qdev_prop_uint8, uint8_t),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void rxicu_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = rxicu_realize;
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dc->vmsd = &vmstate_rxicu;
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device_class_set_props(dc, rxicu_properties);
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}
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static const TypeInfo rxicu_info = {
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.name = TYPE_RX_ICU,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(RXICUState),
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.instance_init = rxicu_init,
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.instance_finalize = rxicu_fini,
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.class_init = rxicu_class_init,
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};
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static void rxicu_register_types(void)
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{
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type_register_static(&rxicu_info);
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}
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type_init(rxicu_register_types)
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